| Message ID | 20220925143743.17636-1-teik.heng.chong@intel.com |
|---|---|
| State | Needs Review / ACK, archived |
| Delegated to: | Marek Vasut |
| Headers | show |
| Series | configs: socfpga: Add CONFIG_NET_RANDOM_ETHADDR=y to SOCFPGA defconfig | expand |
On 9/25/22 09:37, teik.heng.chong@intel.com wrote: > From: Tien Fong Chee <tien.fong.chee@intel.com> > > Ethernet initialization is only work with properly set MAC addresses. > Hence, this config is required to create the random MAC addresses > for Ethernet initialization. > > Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> > Signed-off-by: Teik Heng Chong <teik.heng.chong@intel.com> > --- > configs/socfpga_arria10_defconfig | 1 + > configs/socfpga_arria5_defconfig | 1 + > configs/socfpga_cyclone5_defconfig | 1 + > 3 files changed, 3 insertions(+) > > diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig > index 3eac3dfa5d..53c01ff659 100644 > --- a/configs/socfpga_arria10_defconfig > +++ b/configs/socfpga_arria10_defconfig > @@ -60,6 +60,7 @@ CONFIG_PHY_MICREL=y > CONFIG_PHY_MICREL_KSZ90X1=y > CONFIG_ETH_DESIGNWARE=y > CONFIG_MII=y > +CONFIG_NET_RANDOM_ETHADDR=y > CONFIG_SPI=y > CONFIG_TIMER=y > CONFIG_SPL_TIMER=y > diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig > index dbadb3d49a..da25aa9154 100644 > --- a/configs/socfpga_arria5_defconfig > +++ b/configs/socfpga_arria5_defconfig > @@ -63,6 +63,7 @@ CONFIG_PHY_MICREL=y > CONFIG_PHY_MICREL_KSZ90X1=y > CONFIG_ETH_DESIGNWARE=y > CONFIG_MII=y > +CONFIG_NET_RANDOM_ETHADDR=y > CONFIG_DM_RESET=y > CONFIG_SPI=y > CONFIG_CADENCE_QSPI=y > diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig > index 4fd14d2e2c..508bfe31fc 100644 > --- a/configs/socfpga_cyclone5_defconfig > +++ b/configs/socfpga_cyclone5_defconfig > @@ -64,6 +64,7 @@ CONFIG_PHY_MICREL=y > CONFIG_PHY_MICREL_KSZ90X1=y > CONFIG_ETH_DESIGNWARE=y > CONFIG_MII=y > +CONFIG_NET_RANDOM_ETHADDR=y > CONFIG_DM_RESET=y > CONFIG_SPI=y > CONFIG_CADENCE_QSPI=y Acked-by: Dinh Nguyen <dinguyen@kernel.org>
diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 3eac3dfa5d..53c01ff659 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -60,6 +60,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPI=y CONFIG_TIMER=y CONFIG_SPL_TIMER=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index dbadb3d49a..da25aa9154 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -63,6 +63,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_RESET=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 4fd14d2e2c..508bfe31fc 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -64,6 +64,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_DM_RESET=y CONFIG_SPI=y CONFIG_CADENCE_QSPI=y