diff mbox series

[v2] ARM: dts: rainier,everest: Move reserved memory regions

Message ID 20220916195535.1020185-1-anoo@linux.ibm.com
State New
Headers show
Series [v2] ARM: dts: rainier,everest: Move reserved memory regions | expand

Commit Message

Adriana Kobylak Sept. 16, 2022, 7:55 p.m. UTC 
From: Adriana Kobylak <anoo@us.ibm.com>

Move the reserved regions to account for a decrease in DRAM when ECC is
enabled. ECC takes 1/9th of memory.

Running on HW with ECC off, u-boot prints:
DRAM:  already initialized, 1008 MiB (capacity:1024 MiB, VGA:16 MiB, ECC:off)

And with ECC on, u-boot prints:
DRAM:  already initialized, 896 MiB (capacity:1024 MiB, VGA:16 MiB, ECC:on, ECC size:896 MiB)

This implies that MCR54 is configured for ECC to be bounded at the
bottom of a 16MiB VGA memory region:

1024MiB - 16MiB (VGA) = 1008MiB
1008MiB / 9 (for ECC) = 112MiB
1008MiB - 112MiB = 896MiB (available DRAM)

The flash_memory region currently starts at offset 896MiB:
0xb8000000 (flash_memory offset) - 0x80000000 (base memory address) = 0x38000000 = 896MiB

This is the end of the available DRAM with ECC enabled and therefore it
needs to be moved.

Since the flash_memory is 64MiB in size and needs to be 64MiB aligned,
it can just be moved up by 64MiB and would sit right at the end of the
available DRAM buffer.

The ramoops region currently follows the flash_memory, but it can be
moved to sit above flash_memory which would minimize the address-space
fragmentation.

Signed-off-by: Adriana Kobylak <anoo@us.ibm.com>
---
 arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts | 17 ++++++++---------
 arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 16 +++++++++-------
 2 files changed, 17 insertions(+), 16 deletions(-)

Comments

Andrew Jeffery Sept. 21, 2022, 1:09 a.m. UTC | #1 
On Sat, 17 Sep 2022, at 05:25, Adriana Kobylak wrote:
> From: Adriana Kobylak <anoo@us.ibm.com>
>
> Move the reserved regions to account for a decrease in DRAM when ECC is
> enabled. ECC takes 1/9th of memory.
>
> Running on HW with ECC off, u-boot prints:
> DRAM:  already initialized, 1008 MiB (capacity:1024 MiB, VGA:16 MiB, ECC:off)
>
> And with ECC on, u-boot prints:
> DRAM:  already initialized, 896 MiB (capacity:1024 MiB, VGA:16 MiB, 
> ECC:on, ECC size:896 MiB)
>
> This implies that MCR54 is configured for ECC to be bounded at the
> bottom of a 16MiB VGA memory region:
>
> 1024MiB - 16MiB (VGA) = 1008MiB
> 1008MiB / 9 (for ECC) = 112MiB
> 1008MiB - 112MiB = 896MiB (available DRAM)
>
> The flash_memory region currently starts at offset 896MiB:
> 0xb8000000 (flash_memory offset) - 0x80000000 (base memory address) = 
> 0x38000000 = 896MiB
>
> This is the end of the available DRAM with ECC enabled and therefore it
> needs to be moved.
>
> Since the flash_memory is 64MiB in size and needs to be 64MiB aligned,
> it can just be moved up by 64MiB and would sit right at the end of the
> available DRAM buffer.
>
> The ramoops region currently follows the flash_memory, but it can be
> moved to sit above flash_memory which would minimize the address-space
> fragmentation.
>
> Signed-off-by: Adriana Kobylak <anoo@us.ibm.com>

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts
index 1bba5ad7378e..3bdd79506704 100644
--- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts
@@ -162,16 +162,9 @@  reserved-memory {
 		#size-cells = <1>;
 		ranges;
 
-		/* LPC FW cycle bridge region requires natural alignment */
-		flash_memory: region@b8000000 {
-			no-map;
-			reg = <0xb8000000 0x04000000>; /* 64M */
-		};
-
-		/* 48MB region from the end of flash to start of vga memory */
-		ramoops@bc000000 {
+		ramoops@b3e00000 {
 			compatible = "ramoops";
-			reg = <0xbc000000 0x200000>; /* 16 * (4 * 0x8000) */
+			reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
 			record-size = <0x8000>;
 			console-size = <0x8000>;
 			ftrace-size = <0x8000>;
@@ -179,6 +172,12 @@  ramoops@bc000000 {
 			max-reason = <3>; /* KMSG_DUMP_EMERG */
 		};
 
+		/* LPC FW cycle bridge region requires natural alignment */
+		flash_memory: region@b4000000 {
+			no-map;
+			reg = <0xb4000000 0x04000000>; /* 64M */
+		};
+
 		/* VGA region is dictated by hardware strapping */
 		vga_memory: region@bf000000 {
 			no-map;
diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
index 8bd2f441b159..e1cb3c88368a 100644
--- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
@@ -95,14 +95,9 @@  reserved-memory {
 		#size-cells = <1>;
 		ranges;
 
-		flash_memory: region@b8000000 {
-			no-map;
-			reg = <0xb8000000 0x04000000>; /* 64M */
-		};
-
-		ramoops@bc000000 {
+		ramoops@b3e00000 {
 			compatible = "ramoops";
-			reg = <0xbc000000 0x200000>; /* 16 * (4 * 0x8000) */
+			reg = <0xb3e00000 0x200000>; /* 16 * (4 * 0x8000) */
 			record-size = <0x8000>;
 			console-size = <0x8000>;
 			ftrace-size = <0x8000>;
@@ -110,6 +105,13 @@  ramoops@bc000000 {
 			max-reason = <3>; /* KMSG_DUMP_EMERG */
 		};
 
+		/* LPC FW cycle bridge region requires natural alignment */
+		flash_memory: region@b4000000 {
+			no-map;
+			reg = <0xb4000000 0x04000000>; /* 64M */
+		};
+
+		/* VGA region is dictated by hardware strapping */
 		vga_memory: region@bf000000 {
 			no-map;
 			compatible = "shared-dma-pool";