Message ID | 20220822184701.25246-18-Sergey.Semin@baikalelectronics.ru |
---|---|
State | New |
Headers | show |
Series | PCI: dwc: Add generic resources and Baikal-T1 support | expand |
Hi Serge,
I love your patch! Yet something to improve:
[auto build test ERROR on helgaas-pci/next]
[also build test ERROR on robh/for-next linus/master v6.0-rc2 next-20220822]
[cannot apply to krzk-dt/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Serge-Semin/PCI-dwc-Add-generic-resources-and-Baikal-T1-support/20220823-025041
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: openrisc-randconfig-r001-20220821 (https://download.01.org/0day-ci/archive/20220823/202208230934.dgkY2hhH-lkp@intel.com/config)
compiler: or1k-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/224f55689ef22eddaeb641cf793de934a60e1be9
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Serge-Semin/PCI-dwc-Add-generic-resources-and-Baikal-T1-support/20220823-025041
git checkout 224f55689ef22eddaeb641cf793de934a60e1be9
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=openrisc SHELL=/bin/bash drivers/pci/controller/dwc/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/pci/controller/dwc/pcie-designware-ep.c: In function 'dw_pcie_ep_init':
>> drivers/pci/controller/dwc/pcie-designware-ep.c:734:35: error: 'np' undeclared (first use in this function); did you mean 'ep'?
734 | ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
| ^~
| ep
drivers/pci/controller/dwc/pcie-designware-ep.c:734:35: note: each undeclared identifier is reported only once for each function it appears in
vim +734 drivers/pci/controller/dwc/pcie-designware-ep.c
e966f7390da935e drivers/pci/controller/dwc/pcie-designware-ep.c Vidya Sagar 2020-02-17 678
e966f7390da935e drivers/pci/controller/dwc/pcie-designware-ep.c Vidya Sagar 2020-02-17 679 int dw_pcie_ep_init(struct dw_pcie_ep *ep)
e966f7390da935e drivers/pci/controller/dwc/pcie-designware-ep.c Vidya Sagar 2020-02-17 680 {
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 681 int ret;
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 682 void *addr;
47a062609a30d82 drivers/pci/controller/dwc/pcie-designware-ep.c Xiaowei Bao 2020-09-18 683 u8 func_no;
a0fd361db8e508b drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 684 struct resource *res;
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 685 struct pci_epc *epc;
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 686 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 687 struct device *dev = pci->dev;
a0fd361db8e508b drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 688 struct platform_device *pdev = to_platform_device(dev);
e966f7390da935e drivers/pci/controller/dwc/pcie-designware-ep.c Vidya Sagar 2020-02-17 689 const struct pci_epc_features *epc_features;
47a062609a30d82 drivers/pci/controller/dwc/pcie-designware-ep.c Xiaowei Bao 2020-09-18 690 struct dw_pcie_ep_func *ep_func;
47a062609a30d82 drivers/pci/controller/dwc/pcie-designware-ep.c Xiaowei Bao 2020-09-18 691
47a062609a30d82 drivers/pci/controller/dwc/pcie-designware-ep.c Xiaowei Bao 2020-09-18 692 INIT_LIST_HEAD(&ep->func_list);
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 693
224f55689ef22ed drivers/pci/controller/dwc/pcie-designware-ep.c Serge Semin 2022-08-22 694 ret = dw_pcie_get_resources(pci);
224f55689ef22ed drivers/pci/controller/dwc/pcie-designware-ep.c Serge Semin 2022-08-22 695 if (ret)
224f55689ef22ed drivers/pci/controller/dwc/pcie-designware-ep.c Serge Semin 2022-08-22 696 return ret;
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 697
a0fd361db8e508b drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 698 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
a0fd361db8e508b drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 699 if (!res)
a0fd361db8e508b drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 700 return -EINVAL;
a0fd361db8e508b drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 701
a0fd361db8e508b drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 702 ep->phys_base = res->start;
a0fd361db8e508b drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 703 ep->addr_size = resource_size(res);
a0fd361db8e508b drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 704
13e9d3900c20247 drivers/pci/controller/dwc/pcie-designware-ep.c Serge Semin 2022-06-24 705 dw_pcie_version_detect(pci);
13e9d3900c20247 drivers/pci/controller/dwc/pcie-designware-ep.c Serge Semin 2022-06-24 706
e3dc79adfac96d7 drivers/pci/controller/dwc/pcie-designware-ep.c Serge Semin 2022-06-24 707 dw_pcie_iatu_detect(pci);
e3dc79adfac96d7 drivers/pci/controller/dwc/pcie-designware-ep.c Serge Semin 2022-06-24 708
6be6f8529bd7f3e drivers/pci/controller/dwc/pcie-designware-ep.c Christophe JAILLET 2022-07-09 709 ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows,
ad4a5becc689c3f drivers/pci/dwc/pcie-designware-ep.c Niklas Cassel 2017-12-14 710 GFP_KERNEL);
ad4a5becc689c3f drivers/pci/dwc/pcie-designware-ep.c Niklas Cassel 2017-12-14 711 if (!ep->ib_window_map)
ad4a5becc689c3f drivers/pci/dwc/pcie-designware-ep.c Niklas Cassel 2017-12-14 712 return -ENOMEM;
ad4a5becc689c3f drivers/pci/dwc/pcie-designware-ep.c Niklas Cassel 2017-12-14 713
6be6f8529bd7f3e drivers/pci/controller/dwc/pcie-designware-ep.c Christophe JAILLET 2022-07-09 714 ep->ob_window_map = devm_bitmap_zalloc(dev, pci->num_ob_windows,
ad4a5becc689c3f drivers/pci/dwc/pcie-designware-ep.c Niklas Cassel 2017-12-14 715 GFP_KERNEL);
ad4a5becc689c3f drivers/pci/dwc/pcie-designware-ep.c Niklas Cassel 2017-12-14 716 if (!ep->ob_window_map)
ad4a5becc689c3f drivers/pci/dwc/pcie-designware-ep.c Niklas Cassel 2017-12-14 717 return -ENOMEM;
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 718
9ca17af552bcd28 drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 719 addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t),
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 720 GFP_KERNEL);
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 721 if (!addr)
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 722 return -ENOMEM;
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 723 ep->outbound_addr = addr;
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 724
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 725 epc = devm_pci_epc_create(dev, &epc_ops);
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 726 if (IS_ERR(epc)) {
b4a8a51caf7de47 drivers/pci/dwc/pcie-designware-ep.c Gustavo Pimentel 2018-05-14 727 dev_err(dev, "Failed to create epc device\n");
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 728 return PTR_ERR(epc);
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 729 }
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 730
4e965ede1856ed6 drivers/pci/controller/dwc/pcie-designware-ep.c Gustavo Pimentel 2018-07-19 731 ep->epc = epc;
4e965ede1856ed6 drivers/pci/controller/dwc/pcie-designware-ep.c Gustavo Pimentel 2018-07-19 732 epc_set_drvdata(epc, ep);
4e965ede1856ed6 drivers/pci/controller/dwc/pcie-designware-ep.c Gustavo Pimentel 2018-07-19 733
f8aed6ec624fb43 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 @734 ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
Hi Serge,
I love your patch! Yet something to improve:
[auto build test ERROR on helgaas-pci/next]
[also build test ERROR on robh/for-next linus/master v6.0-rc2 next-20220822]
[cannot apply to krzk-dt/for-next]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/Serge-Semin/PCI-dwc-Add-generic-resources-and-Baikal-T1-support/20220823-025041
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: x86_64-randconfig-a001-20220822 (https://download.01.org/0day-ci/archive/20220823/202208231433.fakKI8V3-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/224f55689ef22eddaeb641cf793de934a60e1be9
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Serge-Semin/PCI-dwc-Add-generic-resources-and-Baikal-T1-support/20220823-025041
git checkout 224f55689ef22eddaeb641cf793de934a60e1be9
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=x86_64 SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/pci/controller/dwc/pcie-designware-ep.c:734:28: error: use of undeclared identifier 'np'
ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
^
1 error generated.
vim +/np +734 drivers/pci/controller/dwc/pcie-designware-ep.c
e966f7390da935 drivers/pci/controller/dwc/pcie-designware-ep.c Vidya Sagar 2020-02-17 678
e966f7390da935 drivers/pci/controller/dwc/pcie-designware-ep.c Vidya Sagar 2020-02-17 679 int dw_pcie_ep_init(struct dw_pcie_ep *ep)
e966f7390da935 drivers/pci/controller/dwc/pcie-designware-ep.c Vidya Sagar 2020-02-17 680 {
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 681 int ret;
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 682 void *addr;
47a062609a30d8 drivers/pci/controller/dwc/pcie-designware-ep.c Xiaowei Bao 2020-09-18 683 u8 func_no;
a0fd361db8e508 drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 684 struct resource *res;
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 685 struct pci_epc *epc;
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 686 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 687 struct device *dev = pci->dev;
a0fd361db8e508 drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 688 struct platform_device *pdev = to_platform_device(dev);
e966f7390da935 drivers/pci/controller/dwc/pcie-designware-ep.c Vidya Sagar 2020-02-17 689 const struct pci_epc_features *epc_features;
47a062609a30d8 drivers/pci/controller/dwc/pcie-designware-ep.c Xiaowei Bao 2020-09-18 690 struct dw_pcie_ep_func *ep_func;
47a062609a30d8 drivers/pci/controller/dwc/pcie-designware-ep.c Xiaowei Bao 2020-09-18 691
47a062609a30d8 drivers/pci/controller/dwc/pcie-designware-ep.c Xiaowei Bao 2020-09-18 692 INIT_LIST_HEAD(&ep->func_list);
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 693
224f55689ef22e drivers/pci/controller/dwc/pcie-designware-ep.c Serge Semin 2022-08-22 694 ret = dw_pcie_get_resources(pci);
224f55689ef22e drivers/pci/controller/dwc/pcie-designware-ep.c Serge Semin 2022-08-22 695 if (ret)
224f55689ef22e drivers/pci/controller/dwc/pcie-designware-ep.c Serge Semin 2022-08-22 696 return ret;
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 697
a0fd361db8e508 drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 698 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
a0fd361db8e508 drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 699 if (!res)
a0fd361db8e508 drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 700 return -EINVAL;
a0fd361db8e508 drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 701
a0fd361db8e508 drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 702 ep->phys_base = res->start;
a0fd361db8e508 drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 703 ep->addr_size = resource_size(res);
a0fd361db8e508 drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 704
13e9d3900c2024 drivers/pci/controller/dwc/pcie-designware-ep.c Serge Semin 2022-06-24 705 dw_pcie_version_detect(pci);
13e9d3900c2024 drivers/pci/controller/dwc/pcie-designware-ep.c Serge Semin 2022-06-24 706
e3dc79adfac96d drivers/pci/controller/dwc/pcie-designware-ep.c Serge Semin 2022-06-24 707 dw_pcie_iatu_detect(pci);
e3dc79adfac96d drivers/pci/controller/dwc/pcie-designware-ep.c Serge Semin 2022-06-24 708
6be6f8529bd7f3 drivers/pci/controller/dwc/pcie-designware-ep.c Christophe JAILLET 2022-07-09 709 ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows,
ad4a5becc689c3 drivers/pci/dwc/pcie-designware-ep.c Niklas Cassel 2017-12-14 710 GFP_KERNEL);
ad4a5becc689c3 drivers/pci/dwc/pcie-designware-ep.c Niklas Cassel 2017-12-14 711 if (!ep->ib_window_map)
ad4a5becc689c3 drivers/pci/dwc/pcie-designware-ep.c Niklas Cassel 2017-12-14 712 return -ENOMEM;
ad4a5becc689c3 drivers/pci/dwc/pcie-designware-ep.c Niklas Cassel 2017-12-14 713
6be6f8529bd7f3 drivers/pci/controller/dwc/pcie-designware-ep.c Christophe JAILLET 2022-07-09 714 ep->ob_window_map = devm_bitmap_zalloc(dev, pci->num_ob_windows,
ad4a5becc689c3 drivers/pci/dwc/pcie-designware-ep.c Niklas Cassel 2017-12-14 715 GFP_KERNEL);
ad4a5becc689c3 drivers/pci/dwc/pcie-designware-ep.c Niklas Cassel 2017-12-14 716 if (!ep->ob_window_map)
ad4a5becc689c3 drivers/pci/dwc/pcie-designware-ep.c Niklas Cassel 2017-12-14 717 return -ENOMEM;
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 718
9ca17af552bcd2 drivers/pci/controller/dwc/pcie-designware-ep.c Rob Herring 2020-11-05 719 addr = devm_kcalloc(dev, pci->num_ob_windows, sizeof(phys_addr_t),
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 720 GFP_KERNEL);
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 721 if (!addr)
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 722 return -ENOMEM;
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 723 ep->outbound_addr = addr;
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 724
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 725 epc = devm_pci_epc_create(dev, &epc_ops);
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 726 if (IS_ERR(epc)) {
b4a8a51caf7de4 drivers/pci/dwc/pcie-designware-ep.c Gustavo Pimentel 2018-05-14 727 dev_err(dev, "Failed to create epc device\n");
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 728 return PTR_ERR(epc);
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 729 }
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 730
4e965ede1856ed drivers/pci/controller/dwc/pcie-designware-ep.c Gustavo Pimentel 2018-07-19 731 ep->epc = epc;
4e965ede1856ed drivers/pci/controller/dwc/pcie-designware-ep.c Gustavo Pimentel 2018-07-19 732 epc_set_drvdata(epc, ep);
4e965ede1856ed drivers/pci/controller/dwc/pcie-designware-ep.c Gustavo Pimentel 2018-07-19 733
f8aed6ec624fb4 drivers/pci/dwc/pcie-designware-ep.c Kishon Vijay Abraham I 2017-03-27 @734 ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 237bb01d7852..80a64b63c055 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -13,8 +13,6 @@ #include <linux/pci-epc.h> #include <linux/pci-epf.h> -#include "../../pci.h" - void dw_pcie_ep_linkup(struct dw_pcie_ep *ep) { struct pci_epc *epc = ep->epc; @@ -688,29 +686,14 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) struct dw_pcie *pci = to_dw_pcie_from_ep(ep); struct device *dev = pci->dev; struct platform_device *pdev = to_platform_device(dev); - struct device_node *np = dev->of_node; const struct pci_epc_features *epc_features; struct dw_pcie_ep_func *ep_func; INIT_LIST_HEAD(&ep->func_list); - if (!pci->dbi_base) { - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); - pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pci->dbi_base)) - return PTR_ERR(pci->dbi_base); - } - - if (!pci->dbi_base2) { - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); - if (!res) { - pci->dbi_base2 = pci->dbi_base + SZ_4K; - } else { - pci->dbi_base2 = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pci->dbi_base2)) - return PTR_ERR(pci->dbi_base2); - } - } + ret = dw_pcie_get_resources(pci); + if (ret) + return ret; res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space"); if (!res) @@ -739,9 +722,6 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) return -ENOMEM; ep->outbound_addr = addr; - if (pci->link_gen < 1) - pci->link_gen = of_pci_get_max_link_speed(np); - epc = devm_pci_epc_create(dev, &epc_ops); if (IS_ERR(epc)) { dev_err(dev, "Failed to create epc device\n"); diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index f0959a9a4970..35da6ec41405 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -16,7 +16,6 @@ #include <linux/pci_regs.h> #include <linux/platform_device.h> -#include "../../pci.h" #include "pcie-designware.h" static struct pci_ops dw_pcie_ops; @@ -409,6 +408,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) raw_spin_lock_init(&pp->lock); + ret = dw_pcie_get_resources(pci); + if (ret) + return ret; + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); if (res) { pp->cfg0_size = resource_size(res); @@ -422,13 +425,6 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) return -ENODEV; } - if (!pci->dbi_base) { - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); - pci->dbi_base = devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pci->dbi_base)) - return PTR_ERR(pci->dbi_base); - } - bridge = devm_pci_alloc_host_bridge(dev, 0); if (!bridge) return -ENOMEM; @@ -443,9 +439,6 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->io_base = pci_pio_to_address(win->res->start); } - if (pci->link_gen < 1) - pci->link_gen = of_pci_get_max_link_speed(np); - /* Set default bus ops */ bridge->ops = &dw_pcie_ops; bridge->child_ops = &dw_child_pcie_ops; diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 9d78e7ca61e1..a8436027434d 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -11,6 +11,7 @@ #include <linux/align.h> #include <linux/bitops.h> #include <linux/delay.h> +#include <linux/ioport.h> #include <linux/of.h> #include <linux/of_platform.h> #include <linux/sizes.h> @@ -19,6 +20,59 @@ #include "../../pci.h" #include "pcie-designware.h" +int dw_pcie_get_resources(struct dw_pcie *pci) +{ + struct platform_device *pdev = to_platform_device(pci->dev); + struct device_node *np = dev_of_node(pci->dev); + struct resource *res; + + if (!pci->dbi_base) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi"); + pci->dbi_base = devm_pci_remap_cfg_resource(pci->dev, res); + if (IS_ERR(pci->dbi_base)) + return PTR_ERR(pci->dbi_base); + } + + /* DBI2 is mainly useful for the endpoint controller */ + if (!pci->dbi_base2) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi2"); + if (res) { + pci->dbi_base2 = devm_pci_remap_cfg_resource(pci->dev, res); + if (IS_ERR(pci->dbi_base2)) + return PTR_ERR(pci->dbi_base2); + } else { + pci->dbi_base2 = pci->dbi_base + SZ_4K; + } + } + + /* For non-unrolled iATU/eDMA platforms this range will be ignored */ + if (!pci->atu_base) { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); + if (res) { + pci->atu_size = resource_size(res); + pci->atu_base = devm_ioremap_resource(pci->dev, res); + if (IS_ERR(pci->atu_base)) + return PTR_ERR(pci->atu_base); + } else { + pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; + } + } + + /* Set a default value suitable for at most 8 in and 8 out windows */ + if (!pci->atu_size) + pci->atu_size = SZ_4K; + + if (pci->link_gen < 1) + pci->link_gen = of_pci_get_max_link_speed(np); + + of_property_read_u32(np, "num-lanes", &pci->num_lanes); + + if (of_property_read_bool(np, "snps,enable-cdm-check")) + dw_pcie_cap_set(pci, CDM_CHECK); + + return 0; +} + void dw_pcie_version_detect(struct dw_pcie *pci) { u32 ver; @@ -639,25 +693,8 @@ static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci) void dw_pcie_iatu_detect(struct dw_pcie *pci) { - struct platform_device *pdev = to_platform_device(pci->dev); - if (dw_pcie_iatu_unroll_enabled(pci)) { dw_pcie_cap_set(pci, IATU_UNROLL); - - if (!pci->atu_base) { - struct resource *res = - platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu"); - if (res) { - pci->atu_size = resource_size(res); - pci->atu_base = devm_ioremap_resource(pci->dev, res); - } - if (!pci->atu_base || IS_ERR(pci->atu_base)) - pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET; - } - - if (!pci->atu_size) - /* Pick a minimal default, enough for 8 in and 8 out windows */ - pci->atu_size = SZ_4K; } else { pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE; pci->atu_size = PCIE_ATU_VIEWPORT_SIZE; @@ -675,7 +712,6 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci) void dw_pcie_setup(struct dw_pcie *pci) { - struct device_node *np = pci->dev->of_node; u32 val; if (pci->link_gen > 0) @@ -703,14 +739,13 @@ void dw_pcie_setup(struct dw_pcie *pci) val |= PORT_LINK_DLL_LINK_EN; dw_pcie_writel_dbi(pci, PCIE_PORT_LINK_CONTROL, val); - if (of_property_read_bool(np, "snps,enable-cdm-check")) { + if (dw_pcie_cap_is(pci, CDM_CHECK)) { val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS); val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS | PCIE_PL_CHK_REG_CHK_REG_START; dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val); } - of_property_read_u32(np, "num-lanes", &pci->num_lanes); if (!pci->num_lanes) { dev_dbg(pci->dev, "Using h/w default number of lanes\n"); return; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 33250d5788e8..d96c888f23ca 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -46,6 +46,7 @@ /* DWC PCIe controller capabilities */ #define DW_PCIE_CAP_IATU_UNROLL 1 +#define DW_PCIE_CAP_CDM_CHECK 2 #define dw_pcie_cap_is(_pci, _cap) \ test_bit(DW_PCIE_CAP_ ## _cap, &(_pci)->caps) @@ -339,6 +340,8 @@ struct dw_pcie { #define to_dw_pcie_from_ep(endpoint) \ container_of((endpoint), struct dw_pcie, ep) +int dw_pcie_get_resources(struct dw_pcie *pci); + void dw_pcie_version_detect(struct dw_pcie *pci); u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);