| Message ID | 243f46dcbef8c089e40e3860c50f5cf2f2699af8.camel@xry111.site |
|---|---|
| State | New |
| Headers | show |
| Series | [v3] loongarch: fix mulsidi3_64bit instruction | expand |
在 2022/7/9 上午10:56, Xi Ruoyao 写道: > v3: Relax scan-assembler pattern in test case mulw_d_w.c. It's because > multiplication is Abelian and the compiler may switch the order of > operands in the future. > -- >8 -- > > (mult (sign_extend:DI rj:SI) (sign_extend:DI rk:SI)) should be > "mulw.d.w", not "mul.d". > > gcc/ChangeLog: > > * config/loongarch/loongarch.md (mulsidi3_64bit): Use mulw.d.w > instead of mul.d. > > gcc/testsuite/ChangeLog: > > * gcc.target/loongarch/mulw_d_w.c: New test. > * gcc.c-torture/execute/mul-sext.c: New test. > --- I think there is no problem with this modification. Thankes!
On Sun, 2022-07-10 at 09:45 +0800, Lulu Cheng wrote: > > 在 2022/7/9 上午10:56, Xi Ruoyao 写道: > > v3: Relax scan-assembler pattern in test case mulw_d_w.c. It's > > because > > multiplication is Abelian and the compiler may switch the order of > > operands in the future. > > -- >8 -- > > > > (mult (sign_extend:DI rj:SI) (sign_extend:DI rk:SI)) should be > > "mulw.d.w", not "mul.d". > > > > gcc/ChangeLog: > > > > * config/loongarch/loongarch.md (mulsidi3_64bit): Use > > mulw.d.w > > instead of mul.d. > > > > gcc/testsuite/ChangeLog: > > > > * gcc.target/loongarch/mulw_d_w.c: New test. > > * gcc.c-torture/execute/mul-sext.c: New test. > > --- > > I think there is no problem with this modification. > > Thankes! > Pushed r13-1591 and r12-8562.
diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md index d3c809e25f3..8f8412fba84 100644 --- a/gcc/config/loongarch/loongarch.md +++ b/gcc/config/loongarch/loongarch.md @@ -621,7 +621,7 @@ (define_insn "mulsidi3_64bit" (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) (sign_extend:DI (match_operand:SI 2 "register_operand" "r"))))] "TARGET_64BIT" - "mul.d\t%0,%1,%2" + "mulw.d.w\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI")]) diff --git a/gcc/testsuite/gcc.c-torture/execute/mul-sext.c b/gcc/testsuite/gcc.c-torture/execute/mul-sext.c new file mode 100644 index 00000000000..8b6800804fb --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/mul-sext.c @@ -0,0 +1,20 @@ +/* { dg-do run } */ + +typedef __INT64_TYPE__ int64_t; +typedef __INT32_TYPE__ int32_t; + +/* f() was misoptimized to a single "mul.d" instruction on LA64. */ +__attribute__((noipa, noinline)) int64_t +f(int64_t a, int64_t b) +{ + return (int64_t)(int32_t)a * (int64_t)(int32_t)b; +} + +int +main() +{ + int64_t a = 0x1145140000000001; + int64_t b = 0x1919810000000001; + if (f(a, b) != 1) + __builtin_abort(); +} diff --git a/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c b/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c new file mode 100644 index 00000000000..4ab7df8836b --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/mulw_d_w.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mabi=lp64d" } */ +/* { dg-final { scan-assembler "mulw.d.w" } } */ + +/* This should be optimized to mulw.d.w for LA64. */ +__attribute__((noipa, noinline)) long +f(long a, long b) +{ + return (long)(int)a * (long)(int)b; +}