Message ID | 20220606150037.338931-7-matheus.ferst@eldorado.org.br |
---|---|
State | New |
Headers | show |
Series | Remove CONFIG_INT128 conditional code from target/ppc/* | expand |
On 06/06/2022 12:00, Matheus Ferst wrote: > And also move the insns to decodetree. > > Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> > --- > target/ppc/helper.h | 4 +-- > target/ppc/insn32.decode | 3 +++ > target/ppc/int_helper.c | 38 +++++++---------------------- > target/ppc/translate/vmx-impl.c.inc | 7 +++--- > target/ppc/translate/vmx-ops.c.inc | 1 - > 5 files changed, 17 insertions(+), 36 deletions(-) > > diff --git a/target/ppc/helper.h b/target/ppc/helper.h > index 1c02ad85e5..04ced6ef70 100644 > --- a/target/ppc/helper.h > +++ b/target/ppc/helper.h > @@ -209,8 +209,8 @@ DEF_HELPER_FLAGS_4(VADDECUQ, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) > DEF_HELPER_FLAGS_4(VADDEUQM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) > DEF_HELPER_FLAGS_3(VADDCUQ, TCG_CALL_NO_RWG, void, avr, avr, avr) > DEF_HELPER_FLAGS_3(VSUBUQM, TCG_CALL_NO_RWG, void, avr, avr, avr) > -DEF_HELPER_FLAGS_4(vsubecuq, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) > -DEF_HELPER_FLAGS_4(vsubeuqm, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) > +DEF_HELPER_FLAGS_4(VSUBECUQ, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) > +DEF_HELPER_FLAGS_4(VSUBEUQM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) > DEF_HELPER_FLAGS_3(vsubcuq, TCG_CALL_NO_RWG, void, avr, avr, avr) > DEF_HELPER_FLAGS_4(vsldoi, TCG_CALL_NO_RWG, void, avr, avr, avr, i32) > DEF_HELPER_FLAGS_3(vextractub, TCG_CALL_NO_RWG, void, avr, avr, i32) > diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode > index a8d3a5a8a1..5e6f3b668e 100644 > --- a/target/ppc/insn32.decode > +++ b/target/ppc/insn32.decode > @@ -558,6 +558,9 @@ VADDECUQ 000100 ..... ..... ..... ..... 111101 @VA > > VSUBUQM 000100 ..... ..... ..... 10100000000 @VX > > +VSUBECUQ 000100 ..... ..... ..... ..... 111111 @VA > +VSUBEUQM 000100 ..... ..... ..... ..... 111110 @VA > + > VEXTSB2W 000100 ..... 10000 ..... 11000000010 @VX_tb > VEXTSH2W 000100 ..... 10001 ..... 11000000010 @VX_tb > VEXTSB2D 000100 ..... 11000 ..... 11000000010 @VX_tb > diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c > index 625cc92a55..c995f8de77 100644 > --- a/target/ppc/int_helper.c > +++ b/target/ppc/int_helper.c > @@ -2244,20 +2244,10 @@ void helper_VSUBUQM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) > r->s128 = int128_sub(a->s128, b->s128); > } > > -void helper_vsubeuqm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) > +void helper_VSUBEUQM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) > { > -#ifdef CONFIG_INT128 > - r->u128 = a->u128 + ~b->u128 + (c->u128 & 1); > -#else > - ppc_avr_t tmp, sum; > - > - avr_qw_not(&tmp, *b); > - avr_qw_add(&sum, *a, tmp); > - > - tmp.VsrD(0) = 0; > - tmp.VsrD(1) = c->VsrD(1) & 1; > - avr_qw_add(r, sum, tmp); > -#endif > + r->s128 = int128_add(int128_add(a->s128, int128_not(b->s128)), > + int128_make64(int128_getlo(c->s128) & 1)); > } > > void helper_vsubcuq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) > @@ -2278,25 +2268,15 @@ void helper_vsubcuq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) > #endif > } > > -void helper_vsubecuq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) > +void helper_VSUBECUQ(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) > { > -#ifdef CONFIG_INT128 > - r->u128 = > - (~a->u128 < ~b->u128) || > - ((c->u128 & 1) && (a->u128 + ~b->u128 == (__uint128_t)-1)); > -#else > - int carry_in = c->VsrD(1) & 1; > - int carry_out = (avr_qw_cmpu(*a, *b) > 0); > - if (!carry_out && carry_in) { > - ppc_avr_t tmp; > - avr_qw_not(&tmp, *b); > - avr_qw_add(&tmp, *a, tmp); > - carry_out = ((tmp.VsrD(0) == -1ull) && (tmp.VsrD(1) == -1ull)); > - } > + Int128 tmp = int128_not(b->s128); > + bool carry_out = int128_ult(int128_not(a->s128), tmp), > + carry_in = int128_getlo(c->s128) & 1; > > + r->VsrD(1) = carry_out || (carry_in && int128_eq(int128_add(a->s128, tmp), > + int128_makes64(-1))); > r->VsrD(0) = 0; > - r->VsrD(1) = carry_out; > -#endif > } > > #define BCD_PLUS_PREF_1 0xC > diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc > index 1e665534c3..671992f7d1 100644 > --- a/target/ppc/translate/vmx-impl.c.inc > +++ b/target/ppc/translate/vmx-impl.c.inc > @@ -1235,10 +1235,6 @@ GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28); > GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29); > GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30); > GEN_VXFORM(vsubcuq, 0, 21); > -GEN_VXFORM3(vsubeuqm, 31, 0); > -GEN_VXFORM3(vsubecuq, 31, 0); > -GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ > - vsubecuq, PPC_NONE, PPC2_ALTIVEC_207) > GEN_VXFORM_TRANS(vsl, 2, 7); > GEN_VXFORM_TRANS(vsr, 2, 11); > GEN_VXFORM_ENV(vpkuhum, 7, 0); > @@ -2568,6 +2564,9 @@ static bool do_va_helper(DisasContext *ctx, arg_VA *a, > TRANS_FLAGS2(ALTIVEC_207, VADDECUQ, do_va_helper, gen_helper_VADDECUQ) > TRANS_FLAGS2(ALTIVEC_207, VADDEUQM, do_va_helper, gen_helper_VADDEUQM) > > +TRANS_FLAGS2(ALTIVEC_207, VSUBEUQM, do_va_helper, gen_helper_VSUBEUQM) > +TRANS_FLAGS2(ALTIVEC_207, VSUBECUQ, do_va_helper, gen_helper_VSUBECUQ) > + > TRANS_FLAGS(ALTIVEC, VPERM, do_va_helper, gen_helper_VPERM) > TRANS_FLAGS2(ISA300, VPERMR, do_va_helper, gen_helper_VPERMR) > > diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc > index 9feef9afee..9395806f3d 100644 > --- a/target/ppc/translate/vmx-ops.c.inc > +++ b/target/ppc/translate/vmx-ops.c.inc > @@ -128,7 +128,6 @@ GEN_VXFORM(vsubshs, 0, 29), > GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE), > GEN_VXFORM_300(bcdtrunc, 0, 20), > GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300), > -GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), > GEN_VXFORM(vsl, 2, 7), > GEN_VXFORM(vsr, 2, 11), > GEN_VXFORM(vpkuhum, 7, 0), > -- > 2.25.1 > > Reviewed-by: Víctor Colombo <victor.colombo@eldorado.org.br>
diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 1c02ad85e5..04ced6ef70 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -209,8 +209,8 @@ DEF_HELPER_FLAGS_4(VADDECUQ, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) DEF_HELPER_FLAGS_4(VADDEUQM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) DEF_HELPER_FLAGS_3(VADDCUQ, TCG_CALL_NO_RWG, void, avr, avr, avr) DEF_HELPER_FLAGS_3(VSUBUQM, TCG_CALL_NO_RWG, void, avr, avr, avr) -DEF_HELPER_FLAGS_4(vsubecuq, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) -DEF_HELPER_FLAGS_4(vsubeuqm, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) +DEF_HELPER_FLAGS_4(VSUBECUQ, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) +DEF_HELPER_FLAGS_4(VSUBEUQM, TCG_CALL_NO_RWG, void, avr, avr, avr, avr) DEF_HELPER_FLAGS_3(vsubcuq, TCG_CALL_NO_RWG, void, avr, avr, avr) DEF_HELPER_FLAGS_4(vsldoi, TCG_CALL_NO_RWG, void, avr, avr, avr, i32) DEF_HELPER_FLAGS_3(vextractub, TCG_CALL_NO_RWG, void, avr, avr, i32) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index a8d3a5a8a1..5e6f3b668e 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -558,6 +558,9 @@ VADDECUQ 000100 ..... ..... ..... ..... 111101 @VA VSUBUQM 000100 ..... ..... ..... 10100000000 @VX +VSUBECUQ 000100 ..... ..... ..... ..... 111111 @VA +VSUBEUQM 000100 ..... ..... ..... ..... 111110 @VA + VEXTSB2W 000100 ..... 10000 ..... 11000000010 @VX_tb VEXTSH2W 000100 ..... 10001 ..... 11000000010 @VX_tb VEXTSB2D 000100 ..... 11000 ..... 11000000010 @VX_tb diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 625cc92a55..c995f8de77 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -2244,20 +2244,10 @@ void helper_VSUBUQM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) r->s128 = int128_sub(a->s128, b->s128); } -void helper_vsubeuqm(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +void helper_VSUBEUQM(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) { -#ifdef CONFIG_INT128 - r->u128 = a->u128 + ~b->u128 + (c->u128 & 1); -#else - ppc_avr_t tmp, sum; - - avr_qw_not(&tmp, *b); - avr_qw_add(&sum, *a, tmp); - - tmp.VsrD(0) = 0; - tmp.VsrD(1) = c->VsrD(1) & 1; - avr_qw_add(r, sum, tmp); -#endif + r->s128 = int128_add(int128_add(a->s128, int128_not(b->s128)), + int128_make64(int128_getlo(c->s128) & 1)); } void helper_vsubcuq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) @@ -2278,25 +2268,15 @@ void helper_vsubcuq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) #endif } -void helper_vsubecuq(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) +void helper_VSUBECUQ(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c) { -#ifdef CONFIG_INT128 - r->u128 = - (~a->u128 < ~b->u128) || - ((c->u128 & 1) && (a->u128 + ~b->u128 == (__uint128_t)-1)); -#else - int carry_in = c->VsrD(1) & 1; - int carry_out = (avr_qw_cmpu(*a, *b) > 0); - if (!carry_out && carry_in) { - ppc_avr_t tmp; - avr_qw_not(&tmp, *b); - avr_qw_add(&tmp, *a, tmp); - carry_out = ((tmp.VsrD(0) == -1ull) && (tmp.VsrD(1) == -1ull)); - } + Int128 tmp = int128_not(b->s128); + bool carry_out = int128_ult(int128_not(a->s128), tmp), + carry_in = int128_getlo(c->s128) & 1; + r->VsrD(1) = carry_out || (carry_in && int128_eq(int128_add(a->s128, tmp), + int128_makes64(-1))); r->VsrD(0) = 0; - r->VsrD(1) = carry_out; -#endif } #define BCD_PLUS_PREF_1 0xC diff --git a/target/ppc/translate/vmx-impl.c.inc b/target/ppc/translate/vmx-impl.c.inc index 1e665534c3..671992f7d1 100644 --- a/target/ppc/translate/vmx-impl.c.inc +++ b/target/ppc/translate/vmx-impl.c.inc @@ -1235,10 +1235,6 @@ GEN_VXFORM_SAT(vsubsbs, MO_8, sub, sssub, 0, 28); GEN_VXFORM_SAT(vsubshs, MO_16, sub, sssub, 0, 29); GEN_VXFORM_SAT(vsubsws, MO_32, sub, sssub, 0, 30); GEN_VXFORM(vsubcuq, 0, 21); -GEN_VXFORM3(vsubeuqm, 31, 0); -GEN_VXFORM3(vsubecuq, 31, 0); -GEN_VXFORM_DUAL(vsubeuqm, PPC_NONE, PPC2_ALTIVEC_207, \ - vsubecuq, PPC_NONE, PPC2_ALTIVEC_207) GEN_VXFORM_TRANS(vsl, 2, 7); GEN_VXFORM_TRANS(vsr, 2, 11); GEN_VXFORM_ENV(vpkuhum, 7, 0); @@ -2568,6 +2564,9 @@ static bool do_va_helper(DisasContext *ctx, arg_VA *a, TRANS_FLAGS2(ALTIVEC_207, VADDECUQ, do_va_helper, gen_helper_VADDECUQ) TRANS_FLAGS2(ALTIVEC_207, VADDEUQM, do_va_helper, gen_helper_VADDEUQM) +TRANS_FLAGS2(ALTIVEC_207, VSUBEUQM, do_va_helper, gen_helper_VSUBEUQM) +TRANS_FLAGS2(ALTIVEC_207, VSUBECUQ, do_va_helper, gen_helper_VSUBECUQ) + TRANS_FLAGS(ALTIVEC, VPERM, do_va_helper, gen_helper_VPERM) TRANS_FLAGS2(ISA300, VPERMR, do_va_helper, gen_helper_VPERMR) diff --git a/target/ppc/translate/vmx-ops.c.inc b/target/ppc/translate/vmx-ops.c.inc index 9feef9afee..9395806f3d 100644 --- a/target/ppc/translate/vmx-ops.c.inc +++ b/target/ppc/translate/vmx-ops.c.inc @@ -128,7 +128,6 @@ GEN_VXFORM(vsubshs, 0, 29), GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE), GEN_VXFORM_300(bcdtrunc, 0, 20), GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300), -GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207), GEN_VXFORM(vsl, 2, 7), GEN_VXFORM(vsr, 2, 11), GEN_VXFORM(vpkuhum, 7, 0),
And also move the insns to decodetree. Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br> --- target/ppc/helper.h | 4 +-- target/ppc/insn32.decode | 3 +++ target/ppc/int_helper.c | 38 +++++++---------------------- target/ppc/translate/vmx-impl.c.inc | 7 +++--- target/ppc/translate/vmx-ops.c.inc | 1 - 5 files changed, 17 insertions(+), 36 deletions(-)