| Message ID | 20220621233412.506768-1-robert.foss@linaro.org |
|---|---|
| Headers | show |
| Series | SM8350 Display/GPU clock enablement | expand |
On 22.06.2022 01:34, Robert Foss wrote: > Replace &rpmhpd power domain integers with their respective defines > in order to improve legibility. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > arch/arm64/boot/dts/qcom/sm8350.dtsi | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index c0137bdcf94b..52428b6df64e 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -1656,8 +1656,8 @@ mpss: remoteproc@4080000 { > clocks = <&rpmhcc RPMH_CXO_CLK>; > clock-names = "xo"; > > - power-domains = <&rpmhpd 0>, > - <&rpmhpd 12>; > + power-domains = <&rpmhpd SM8350_CX>, > + <&rpmhpd SM8350_MSS>; > power-domain-names = "cx", "mss"; > > interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; > @@ -2167,8 +2167,8 @@ slpi: remoteproc@5c00000 { > clocks = <&rpmhcc RPMH_CXO_CLK>; > clock-names = "xo"; > > - power-domains = <&rpmhpd 4>, > - <&rpmhpd 5>; > + power-domains = <&rpmhpd SM8350_LCX>, > + <&rpmhpd SM8350_LMX>; > power-domain-names = "lcx", "lmx"; > > memory-region = <&pil_slpi_mem>; > @@ -2235,8 +2235,8 @@ cdsp: remoteproc@98900000 { > clocks = <&rpmhcc RPMH_CXO_CLK>; > clock-names = "xo"; > > - power-domains = <&rpmhpd 0>, > - <&rpmhpd 10>; > + power-domains = <&rpmhpd SM8350_CX>, > + <&rpmhpd SM8350_MXC>; > power-domain-names = "cx", "mxc"; > > interconnects = <&compute_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>; > @@ -2540,8 +2540,8 @@ adsp: remoteproc@17300000 { > clocks = <&rpmhcc RPMH_CXO_CLK>; > clock-names = "xo"; > > - power-domains = <&rpmhpd 4>, > - <&rpmhpd 5>; > + power-domains = <&rpmhpd SM8350_LCX>, > + <&rpmhpd SM8350_LMX>; > power-domain-names = "lcx", "lmx"; > > memory-region = <&pil_adsp_mem>;
On 22.06.2022 01:34, Robert Foss wrote: > The GPUCC manages the clocks for the Adreno GPU found on the > sm8350 SoCs. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > --- > > Changes since v1 > - Remove .name assignments for clk_parent_data - Dmitry > - Use ARRAY_SIZE where possible - Dmitry > - Remove commented out code - Dmitry > - Set CLAMP_IO flag for gpu_gx_gdsc - Dmitry > - Assign .parent_hws instead of .hw - Dmitry > > Changes since v2 > - Switch license to dual BSD/GPL - Bjorn > - Add Jonathans SoB - Jonathan > - Add Linaro to copyright statement - Bjorn > - Make .hw.init assignment const - Bjorn > - Extract & deduplicate bi_tcxo parent_data - Bjorn > - Removed further .name assignment - Bjorn > - Move of_device_id declaration - Bjorn > > Changes since v3 > - Change license to BSD/GPL - Rob/Bjorn > - Switch from .fw_name to .index > > Changes since v4 > - Change year of copyright statement > - Change to dual license for header file - Rob > > Changes since since v5 > - Change hex to lower case - Konrad > > > drivers/clk/qcom/Kconfig | 8 + > drivers/clk/qcom/Makefile | 1 + > drivers/clk/qcom/gpucc-sm8350.c | 637 ++++++++++++++++++++++++++++++++ > 3 files changed, 646 insertions(+) > create mode 100644 drivers/clk/qcom/gpucc-sm8350.c > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index bc4dcf356d82..b11235c21952 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -712,6 +712,14 @@ config SM_GPUCC_8250 > Say Y if you want to support graphics controller devices and > functionality such as 3D graphics. > > +config SM_GPUCC_8350 > + tristate "SM8350 Graphics Clock Controller" > + select SM_GCC_8350 > + help > + Support for the graphics clock controller on SM8350 devices. > + Say Y if you want to support graphics controller devices and > + functionality such as 3D graphics. > + > config SM_VIDEOCC_8150 > tristate "SM8150 Video Clock Controller" > select SM_GCC_8150 > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > index 36789f5233ef..ef9c64824424 100644 > --- a/drivers/clk/qcom/Makefile > +++ b/drivers/clk/qcom/Makefile > @@ -101,6 +101,7 @@ obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o > obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o > obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o > obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o > +obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o > obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o > obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o > obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o > diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c > new file mode 100644 > index 000000000000..b7f075b1a81b > --- /dev/null > +++ b/drivers/clk/qcom/gpucc-sm8350.c > @@ -0,0 +1,637 @@ > +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause I don't think you can relicense this code, as Jonathan mentioned in a previous revision [1], this is mostly the downstream driver which was explicitly GPL-2.0-only [2]. > +/* > + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. > + * Copyright (c) 2022, Linaro Limited > + */ > + > +#include <linux/clk.h> > +#include <linux/err.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of_device.h> > +#include <linux/of.h> > +#include <linux/regmap.h> > + > +#include <dt-bindings/clock/qcom,gpucc-sm8350.h> > + > +#include "clk-alpha-pll.h" > +#include "clk-branch.h" > +#include "clk-pll.h" > +#include "clk-rcg.h" > +#include "clk-regmap.h" > +#include "common.h" > +#include "clk-regmap-mux.h" > +#include "clk-regmap-divider.h" > +#include "gdsc.h" > +#include "reset.h" > + > +enum { > + P_BI_TCXO, > + P_GPLL0_OUT_MAIN, > + P_GPLL0_OUT_MAIN_DIV, > + P_GPU_CC_PLL0_OUT_MAIN, > + P_GPU_CC_PLL1_OUT_MAIN, > +}; > + > +static struct pll_vco lucid_5lpe_vco[] = { > + { 249600000, 1750000000, 0 }, > +}; > + > +static const struct alpha_pll_config gpu_cc_pll0_config = { > + .l = 0x18, > + .alpha = 0x6000, > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00002261, > + .config_ctl_hi1_val = 0x2a9a699c, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000000, > + .test_ctl_hi1_val = 0x01800000, > + .user_ctl_val = 0x00000000, > + .user_ctl_hi_val = 0x00000805, > + .user_ctl_hi1_val = 0x00000000, > +}; > + > +static const struct clk_parent_data gpu_cc_parent = { > + .fw_name = "bi_tcxo", > +}; > + > +static struct clk_alpha_pll gpu_cc_pll0 = { > + .offset = 0x0, > + .vco_table = lucid_5lpe_vco, > + .num_vco = ARRAY_SIZE(lucid_5lpe_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > + .clkr = { > + .hw.init = &(const struct clk_init_data){ > + .name = "gpu_cc_pll0", > + .parent_data = &gpu_cc_parent, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_5lpe_ops, > + }, > + }, > +}; > + > +static const struct alpha_pll_config gpu_cc_pll1_config = { > + .l = 0x1A, > + .alpha = 0xAAA, Lowercase hex, please, all throughout the file. The rest looks good. Konrad [1] https://yhbt.net/lore/all/e7935b8e-1e4c-a424-7d77-307e346f507f@marek.ca/ [2] https://github.com/sonyxperiadev/kernel/blob/aosp/LA.UM.9.14.r1/drivers/clk/qcom/gpucc-lahaina.c#L1 > + .config_ctl_val = 0x20485699, > + .config_ctl_hi_val = 0x00002261, > + .config_ctl_hi1_val = 0x2A9A699C, > + .test_ctl_val = 0x00000000, > + .test_ctl_hi_val = 0x00000000, > + .test_ctl_hi1_val = 0x01800000, > + .user_ctl_val = 0x00000000, > + .user_ctl_hi_val = 0x00000805, > + .user_ctl_hi1_val = 0x00000000, > +}; > + > +static struct clk_alpha_pll gpu_cc_pll1 = { > + .offset = 0x100, > + .vco_table = lucid_5lpe_vco, > + .num_vco = ARRAY_SIZE(lucid_5lpe_vco), > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > + .clkr = { > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_pll1", > + .parent_data = &gpu_cc_parent, > + .num_parents = 1, > + .ops = &clk_alpha_pll_lucid_5lpe_ops, > + }, > + }, > +}; > + > +static const struct parent_map gpu_cc_parent_map_0[] = { > + { P_BI_TCXO, 0 }, > + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, > + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, > + { P_GPLL0_OUT_MAIN, 5 }, > + { P_GPLL0_OUT_MAIN_DIV, 6 }, > +}; > + > +static const struct clk_parent_data gpu_cc_parent_data_0[] = { > + gpu_cc_parent, > + { .hw = &gpu_cc_pll0.clkr.hw }, > + { .hw = &gpu_cc_pll1.clkr.hw }, > + { .fw_name = "gcc_gpu_gpll0_clk_src" }, > + { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, > +}; > + > +static const struct parent_map gpu_cc_parent_map_1[] = { > + { P_BI_TCXO, 0 }, > + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, > + { P_GPLL0_OUT_MAIN, 5 }, > + { P_GPLL0_OUT_MAIN_DIV, 6 }, > +}; > + > +static const struct clk_parent_data gpu_cc_parent_data_1[] = { > + gpu_cc_parent, > + { .hw = &gpu_cc_pll1.clkr.hw }, > + { .fw_name = "gcc_gpu_gpll0_clk_src" }, > + { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, > +}; > + > +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { > + F(19200000, P_BI_TCXO, 1, 0, 0), > + F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), > + F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gpu_cc_gmu_clk_src = { > + .cmd_rcgr = 0x1120, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gpu_cc_parent_map_0, > + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_gmu_clk_src", > + .parent_data = gpu_cc_parent_data_0, > + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { > + F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), > + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), > + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), > + { } > +}; > + > +static struct clk_rcg2 gpu_cc_hub_clk_src = { > + .cmd_rcgr = 0x117c, > + .mnd_width = 0, > + .hid_width = 5, > + .parent_map = gpu_cc_parent_map_1, > + .freq_tbl = ftbl_gpu_cc_hub_clk_src, > + .clkr.hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_hub_clk_src", > + .parent_data = gpu_cc_parent_data_1, > + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_rcg2_ops, > + }, > +}; > + > +static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { > + .reg = 0x11c0, > + .shift = 0, > + .width = 4, > + .clkr.hw.init = &(struct clk_init_data) { > + .name = "gpu_cc_hub_ahb_div_clk_src", > + .parent_hws = (const struct clk_hw*[]){ > + &gpu_cc_hub_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_regmap_div_ro_ops, > + }, > +}; > + > +static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { > + .reg = 0x11bc, > + .shift = 0, > + .width = 4, > + .clkr.hw.init = &(struct clk_init_data) { > + .name = "gpu_cc_hub_cx_int_div_clk_src", > + .parent_hws = (const struct clk_hw*[]){ > + &gpu_cc_hub_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_regmap_div_ro_ops, > + }, > +}; > + > +static struct clk_branch gpu_cc_ahb_clk = { > + .halt_reg = 0x1078, > + .halt_check = BRANCH_HALT_DELAY, > + .clkr = { > + .enable_reg = 0x1078, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_ahb_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cb_clk = { > + .halt_reg = 0x1170, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1170, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cb_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_crc_ahb_clk = { > + .halt_reg = 0x107c, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x107c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_crc_ahb_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cx_apb_clk = { > + .halt_reg = 0x1088, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x1088, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cx_apb_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cx_gmu_clk = { > + .halt_reg = 0x1098, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1098, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cx_gmu_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &gpu_cc_gmu_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_aon_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cx_qdss_at_clk = { > + .halt_reg = 0x1080, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x1080, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cx_qdss_at_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cx_qdss_trig_clk = { > + .halt_reg = 0x1094, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x1094, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cx_qdss_trig_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = { > + .halt_reg = 0x1084, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x1084, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cx_qdss_tsctr_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { > + .halt_reg = 0x108c, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x108c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cx_snoc_dvm_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cxo_aon_clk = { > + .halt_reg = 0x1004, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x1004, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cxo_aon_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_cxo_clk = { > + .halt_reg = 0x109c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x109c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_cxo_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_freq_measure_clk = { > + .halt_reg = 0x120c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x120c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_freq_measure_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_gx_gmu_clk = { > + .halt_reg = 0x1064, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1064, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_gx_gmu_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &gpu_cc_gmu_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = { > + .halt_reg = 0x105c, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x105c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_gx_qdss_tsctr_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_gx_vsense_clk = { > + .halt_reg = 0x1058, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x1058, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_gx_vsense_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { > + .halt_reg = 0x5000, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x5000, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_hub_aon_clk = { > + .halt_reg = 0x1178, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1178, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_hub_aon_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &gpu_cc_hub_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_aon_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_hub_cx_int_clk = { > + .halt_reg = 0x1204, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x1204, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_hub_cx_int_clk", > + .parent_hws = (const struct clk_hw*[]){ > + &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, > + }, > + .num_parents = 1, > + .flags = CLK_SET_RATE_PARENT, > + .ops = &clk_branch2_aon_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = { > + .halt_reg = 0x802c, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x802c, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_mnd1x_0_gfx3d_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = { > + .halt_reg = 0x8030, > + .halt_check = BRANCH_HALT, > + .clkr = { > + .enable_reg = 0x8030, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_mnd1x_1_gfx3d_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct clk_branch gpu_cc_sleep_clk = { > + .halt_reg = 0x1090, > + .halt_check = BRANCH_HALT_VOTED, > + .clkr = { > + .enable_reg = 0x1090, > + .enable_mask = BIT(0), > + .hw.init = &(struct clk_init_data){ > + .name = "gpu_cc_sleep_clk", > + .ops = &clk_branch2_ops, > + }, > + }, > +}; > + > +static struct gdsc gpu_cx_gdsc = { > + .gdscr = 0x106c, > + .gds_hw_ctrl = 0x1540, > + .pd = { > + .name = "gpu_cx_gdsc", > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = VOTABLE, > +}; > + > +static struct gdsc gpu_gx_gdsc = { > + .gdscr = 0x100c, > + .clamp_io_ctrl = 0x1508, > + .pd = { > + .name = "gpu_gx_gdsc", > + .power_on = gdsc_gx_do_nothing_enable, > + }, > + .pwrsts = PWRSTS_OFF_ON, > + .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR, > +}; > + > +static struct clk_regmap *gpu_cc_sm8350_clocks[] = { > + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, > + [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr, > + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, > + [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, > + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, > + [GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr, > + [GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr, > + [GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr, > + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, > + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, > + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, > + [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, > + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, > + [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, > + [GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr, > + [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr, > + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, > + [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, > + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, > + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, > + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, > + [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, > + [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr, > + [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr, > + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, > + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, > + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, > +}; > + > +static const struct qcom_reset_map gpu_cc_sm8350_resets[] = { > + [GPUCC_GPU_CC_ACD_BCR] = { 0x1160 }, > + [GPUCC_GPU_CC_CB_BCR] = { 0x116c }, > + [GPUCC_GPU_CC_CX_BCR] = { 0x1068 }, > + [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x1174 }, > + [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 }, > + [GPUCC_GPU_CC_GMU_BCR] = { 0x111c }, > + [GPUCC_GPU_CC_GX_BCR] = { 0x1008 }, > + [GPUCC_GPU_CC_XO_BCR] = { 0x1000 }, > +}; > + > +static struct gdsc *gpu_cc_sm8350_gdscs[] = { > + [GPU_CX_GDSC] = &gpu_cx_gdsc, > + [GPU_GX_GDSC] = &gpu_gx_gdsc, > +}; > + > +static const struct regmap_config gpu_cc_sm8350_regmap_config = { > + .reg_bits = 32, > + .reg_stride = 4, > + .val_bits = 32, > + .max_register = 0x8030, > + .fast_io = true, > +}; > + > +static const struct qcom_cc_desc gpu_cc_sm8350_desc = { > + .config = &gpu_cc_sm8350_regmap_config, > + .clks = gpu_cc_sm8350_clocks, > + .num_clks = ARRAY_SIZE(gpu_cc_sm8350_clocks), > + .resets = gpu_cc_sm8350_resets, > + .num_resets = ARRAY_SIZE(gpu_cc_sm8350_resets), > + .gdscs = gpu_cc_sm8350_gdscs, > + .num_gdscs = ARRAY_SIZE(gpu_cc_sm8350_gdscs), > +}; > + > +static int gpu_cc_sm8350_probe(struct platform_device *pdev) > +{ > + struct regmap *regmap; > + > + regmap = qcom_cc_map(pdev, &gpu_cc_sm8350_desc); > + if (IS_ERR(regmap)) { > + dev_err(&pdev->dev, "Failed to map gpu cc registers\n"); > + return PTR_ERR(regmap); > + } > + > + clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); > + clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); > + > + return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap); > +} > + > +static const struct of_device_id gpu_cc_sm8350_match_table[] = { > + { .compatible = "qcom,sm8350-gpucc" }, > + { } > +}; > +MODULE_DEVICE_TABLE(of, gpu_cc_sm8350_match_table); > + > +static struct platform_driver gpu_cc_sm8350_driver = { > + .probe = gpu_cc_sm8350_probe, > + .driver = { > + .name = "sm8350-gpucc", > + .of_match_table = gpu_cc_sm8350_match_table, > + }, > +}; > + > +static int __init gpu_cc_sm8350_init(void) > +{ > + return platform_driver_register(&gpu_cc_sm8350_driver); > +} > +subsys_initcall(gpu_cc_sm8350_init); > + > +static void __exit gpu_cc_sm8350_exit(void) > +{ > + platform_driver_unregister(&gpu_cc_sm8350_driver); > +} > +module_exit(gpu_cc_sm8350_exit); > + > +MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver"); > +MODULE_LICENSE("GPL v2");
On 22.06.2022 01:34, Robert Foss wrote: > From: Jonathan Marek <jonathan@marek.ca> > > Add support to the SM8350 display clock controller by extending the SM8250 > display clock controller, which is almost identical but has some minor > differences. > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > Signed-off-by: Robert Foss <robert.foss@linaro.org> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- > > Changes since v1 > - Remove comment - Dmitry > > Changes since v2 > - Add my SoB - Bjorn > - Remove CLK_ASSUME_ENABLED_WHEN_UNUSED flag > > Changes since v3 > - Add kconfig dependency on SM_GCC_8350 - Konrad > - Change hex to lowercase - Konrad > - Split from dispcc-sm8250.c implementation > - Switch from .fw_name to .index > > Changes since v4 > - Hex to lowercase - Konrad > - Remove bad match table entries - Konrad > > Changes since v5 > - Reverted split from dispcc-sm8250 > - Re-added tags from v3 > > > drivers/clk/qcom/Kconfig | 4 +-- > drivers/clk/qcom/dispcc-sm8250.c | 60 +++++++++++++++++++++++++++++++- > 2 files changed, 61 insertions(+), 3 deletions(-) > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > index b11235c21952..4c3d1a548b7a 100644 > --- a/drivers/clk/qcom/Kconfig > +++ b/drivers/clk/qcom/Kconfig > @@ -618,11 +618,11 @@ config SM_DISPCC_6125 > splash screen > > config SM_DISPCC_8250 > - tristate "SM8150 and SM8250 Display Clock Controller" > + tristate "SM8150/SM8250/SM8350 Display Clock Controller" > depends on SM_GCC_8150 || SM_GCC_8250 || SM_GCC_8350 > help > Support for the display clock controller on Qualcomm Technologies, Inc > - SM8150 and SM8250 devices. > + SM8150/SM8250/SM8350 devices. > Say Y if you want to support display devices and functionality such as > splash screen. > > diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c > index db9379634fb2..4e101d584115 100644 > --- a/drivers/clk/qcom/dispcc-sm8250.c > +++ b/drivers/clk/qcom/dispcc-sm8250.c > @@ -43,6 +43,10 @@ static struct pll_vco vco_table[] = { > { 249600000, 2000000000, 0 }, > }; > > +static struct pll_vco lucid_5lpe_vco[] = { > + { 249600000, 1750000000, 0 }, > +}; > + > static struct alpha_pll_config disp_cc_pll0_config = { > .l = 0x47, > .alpha = 0xE000, > @@ -1228,6 +1232,7 @@ static const struct of_device_id disp_cc_sm8250_match_table[] = { > { .compatible = "qcom,sc8180x-dispcc" }, > { .compatible = "qcom,sm8150-dispcc" }, > { .compatible = "qcom,sm8250-dispcc" }, > + { .compatible = "qcom,sm8350-dispcc" }, > { } > }; > MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table); > @@ -1258,7 +1263,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) > return PTR_ERR(regmap); > } > > - /* note: trion == lucid, except for the prepare() op */ > + /* Apply differences for SM8150 and SM8350 */ I think both comments should stay, as the one you're adding doesn't explain the BUILD_BUG_ON() Konrad > BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); > if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") || > of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { > @@ -1270,6 +1275,59 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) > disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; > disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; > disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; > + } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) { > + static struct clk_rcg2 * const rcgs[] = { > + &disp_cc_mdss_byte0_clk_src, > + &disp_cc_mdss_byte1_clk_src, > + &disp_cc_mdss_dp_aux1_clk_src, > + &disp_cc_mdss_dp_aux_clk_src, > + &disp_cc_mdss_dp_link1_clk_src, > + &disp_cc_mdss_dp_link_clk_src, > + &disp_cc_mdss_dp_pixel1_clk_src, > + &disp_cc_mdss_dp_pixel2_clk_src, > + &disp_cc_mdss_dp_pixel_clk_src, > + &disp_cc_mdss_esc0_clk_src, > + &disp_cc_mdss_mdp_clk_src, > + &disp_cc_mdss_pclk0_clk_src, > + &disp_cc_mdss_pclk1_clk_src, > + &disp_cc_mdss_rot_clk_src, > + &disp_cc_mdss_vsync_clk_src, > + }; > + static struct clk_regmap_div * const divs[] = { > + &disp_cc_mdss_byte0_div_clk_src, > + &disp_cc_mdss_byte1_div_clk_src, > + &disp_cc_mdss_dp_link1_div_clk_src, > + &disp_cc_mdss_dp_link_div_clk_src, > + }; > + unsigned int i; > + static bool offset_applied; > + > + /* only apply the offsets once (in case of deferred probe) */ > + if (!offset_applied) { > + for (i = 0; i < ARRAY_SIZE(rcgs); i++) > + rcgs[i]->cmd_rcgr -= 4; > + > + for (i = 0; i < ARRAY_SIZE(divs); i++) { > + divs[i]->reg -= 4; > + divs[i]->width = 4; > + } > + > + disp_cc_mdss_ahb_clk.halt_reg -= 4; > + disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4; > + > + offset_applied = true; > + } > + > + disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0; > + > + disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c; > + disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000; > + disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops; > + disp_cc_pll0.vco_table = lucid_5lpe_vco; > + disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c; > + disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000; > + disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops; > + disp_cc_pll1.vco_table = lucid_5lpe_vco; > } > > clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
On 22.06.2022 01:34, Robert Foss wrote: > Add the dispcc clock-controller DT node for sm8350. > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org> Konrad > > Changes since v2 > - Remove interconnect include - Bjorn > > Changes since v3 > - Switch from .fw_name to .index > > Changes since v5 > - Revert .fw_name to .index change > > > arch/arm64/boot/dts/qcom/sm8350.dtsi | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index 52428b6df64e..99464cd1299e 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -4,6 +4,7 @@ > */ > > #include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/clock/qcom,dispcc-sm8350.h> > #include <dt-bindings/clock/qcom,gcc-sm8350.h> > #include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/dma/qcom-gpi.h> > @@ -2525,6 +2526,31 @@ usb_2_dwc3: usb@a800000 { > }; > }; > > + dispcc: clock-controller@af00000 { > + compatible = "qcom,sm8350-dispcc"; > + reg = <0 0x0af00000 0 0x10000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>; > + clock-names = "bi_tcxo", > + "dsi0_phy_pll_out_byteclk", > + "dsi0_phy_pll_out_dsiclk", > + "dsi1_phy_pll_out_byteclk", > + "dsi1_phy_pll_out_dsiclk", > + "dp_phy_pll_link_clk", > + "dp_phy_pll_vco_div_clk"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + > + power-domains = <&rpmhpd SM8350_MMCX>; > + power-domain-names = "mmcx"; > + }; > + > adsp: remoteproc@17300000 { > compatible = "qcom,sm8350-adsp-pas"; > reg = <0 0x17300000 0 0x100>;
On Wed, 22 Jun 2022 at 12:20, Konrad Dybcio <konrad.dybcio@somainline.org> wrote: > > > > On 22.06.2022 01:34, Robert Foss wrote: > > The GPUCC manages the clocks for the Adreno GPU found on the > > sm8350 SoCs. > > > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > > --- > > > > Changes since v1 > > - Remove .name assignments for clk_parent_data - Dmitry > > - Use ARRAY_SIZE where possible - Dmitry > > - Remove commented out code - Dmitry > > - Set CLAMP_IO flag for gpu_gx_gdsc - Dmitry > > - Assign .parent_hws instead of .hw - Dmitry > > > > Changes since v2 > > - Switch license to dual BSD/GPL - Bjorn > > - Add Jonathans SoB - Jonathan > > - Add Linaro to copyright statement - Bjorn > > - Make .hw.init assignment const - Bjorn > > - Extract & deduplicate bi_tcxo parent_data - Bjorn > > - Removed further .name assignment - Bjorn > > - Move of_device_id declaration - Bjorn > > > > Changes since v3 > > - Change license to BSD/GPL - Rob/Bjorn > > - Switch from .fw_name to .index > > > > Changes since v4 > > - Change year of copyright statement > > - Change to dual license for header file - Rob > > > > Changes since since v5 > > - Change hex to lower case - Konrad > > > > > > drivers/clk/qcom/Kconfig | 8 + > > drivers/clk/qcom/Makefile | 1 + > > drivers/clk/qcom/gpucc-sm8350.c | 637 ++++++++++++++++++++++++++++++++ > > 3 files changed, 646 insertions(+) > > create mode 100644 drivers/clk/qcom/gpucc-sm8350.c > > > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > > index bc4dcf356d82..b11235c21952 100644 > > --- a/drivers/clk/qcom/Kconfig > > +++ b/drivers/clk/qcom/Kconfig > > @@ -712,6 +712,14 @@ config SM_GPUCC_8250 > > Say Y if you want to support graphics controller devices and > > functionality such as 3D graphics. > > > > +config SM_GPUCC_8350 > > + tristate "SM8350 Graphics Clock Controller" > > + select SM_GCC_8350 > > + help > > + Support for the graphics clock controller on SM8350 devices. > > + Say Y if you want to support graphics controller devices and > > + functionality such as 3D graphics. > > + > > config SM_VIDEOCC_8150 > > tristate "SM8150 Video Clock Controller" > > select SM_GCC_8150 > > diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile > > index 36789f5233ef..ef9c64824424 100644 > > --- a/drivers/clk/qcom/Makefile > > +++ b/drivers/clk/qcom/Makefile > > @@ -101,6 +101,7 @@ obj-$(CONFIG_SM_GCC_8450) += gcc-sm8450.o > > obj-$(CONFIG_SM_GPUCC_6350) += gpucc-sm6350.o > > obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o > > obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o > > +obj-$(CONFIG_SM_GPUCC_8350) += gpucc-sm8350.o > > obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o > > obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o > > obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o > > diff --git a/drivers/clk/qcom/gpucc-sm8350.c b/drivers/clk/qcom/gpucc-sm8350.c > > new file mode 100644 > > index 000000000000..b7f075b1a81b > > --- /dev/null > > +++ b/drivers/clk/qcom/gpucc-sm8350.c > > @@ -0,0 +1,637 @@ > > +// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause > I don't think you can relicense this code, as Jonathan mentioned in a previous revision [1], this is mostly the downstream driver which was explicitly GPL-2.0-only [2]. Ack > > > > +/* > > + * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. > > + * Copyright (c) 2022, Linaro Limited > > + */ > > + > > +#include <linux/clk.h> > > +#include <linux/err.h> > > +#include <linux/kernel.h> > > +#include <linux/module.h> > > +#include <linux/of_device.h> > > +#include <linux/of.h> > > +#include <linux/regmap.h> > > + > > +#include <dt-bindings/clock/qcom,gpucc-sm8350.h> > > + > > +#include "clk-alpha-pll.h" > > +#include "clk-branch.h" > > +#include "clk-pll.h" > > +#include "clk-rcg.h" > > +#include "clk-regmap.h" > > +#include "common.h" > > +#include "clk-regmap-mux.h" > > +#include "clk-regmap-divider.h" > > +#include "gdsc.h" > > +#include "reset.h" > > + > > +enum { > > + P_BI_TCXO, > > + P_GPLL0_OUT_MAIN, > > + P_GPLL0_OUT_MAIN_DIV, > > + P_GPU_CC_PLL0_OUT_MAIN, > > + P_GPU_CC_PLL1_OUT_MAIN, > > +}; > > + > > +static struct pll_vco lucid_5lpe_vco[] = { > > + { 249600000, 1750000000, 0 }, > > +}; > > + > > +static const struct alpha_pll_config gpu_cc_pll0_config = { > > + .l = 0x18, > > + .alpha = 0x6000, > > + .config_ctl_val = 0x20485699, > > + .config_ctl_hi_val = 0x00002261, > > + .config_ctl_hi1_val = 0x2a9a699c, > > + .test_ctl_val = 0x00000000, > > + .test_ctl_hi_val = 0x00000000, > > + .test_ctl_hi1_val = 0x01800000, > > + .user_ctl_val = 0x00000000, > > + .user_ctl_hi_val = 0x00000805, > > + .user_ctl_hi1_val = 0x00000000, > > +}; > > + > > +static const struct clk_parent_data gpu_cc_parent = { > > + .fw_name = "bi_tcxo", > > +}; > > + > > +static struct clk_alpha_pll gpu_cc_pll0 = { > > + .offset = 0x0, > > + .vco_table = lucid_5lpe_vco, > > + .num_vco = ARRAY_SIZE(lucid_5lpe_vco), > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > > + .clkr = { > > + .hw.init = &(const struct clk_init_data){ > > + .name = "gpu_cc_pll0", > > + .parent_data = &gpu_cc_parent, > > + .num_parents = 1, > > + .ops = &clk_alpha_pll_lucid_5lpe_ops, > > + }, > > + }, > > +}; > > + > > +static const struct alpha_pll_config gpu_cc_pll1_config = { > > + .l = 0x1A, > > + .alpha = 0xAAA, > Lowercase hex, please, all throughout the file. Ack. > > The rest looks good. > > > Konrad > > [1] https://yhbt.net/lore/all/e7935b8e-1e4c-a424-7d77-307e346f507f@marek.ca/ > [2] https://github.com/sonyxperiadev/kernel/blob/aosp/LA.UM.9.14.r1/drivers/clk/qcom/gpucc-lahaina.c#L1 > > > + .config_ctl_val = 0x20485699, > > + .config_ctl_hi_val = 0x00002261, > > + .config_ctl_hi1_val = 0x2A9A699C, > > + .test_ctl_val = 0x00000000, > > + .test_ctl_hi_val = 0x00000000, > > + .test_ctl_hi1_val = 0x01800000, > > + .user_ctl_val = 0x00000000, > > + .user_ctl_hi_val = 0x00000805, > > + .user_ctl_hi1_val = 0x00000000, > > +}; > > + > > +static struct clk_alpha_pll gpu_cc_pll1 = { > > + .offset = 0x100, > > + .vco_table = lucid_5lpe_vco, > > + .num_vco = ARRAY_SIZE(lucid_5lpe_vco), > > + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID], > > + .clkr = { > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_pll1", > > + .parent_data = &gpu_cc_parent, > > + .num_parents = 1, > > + .ops = &clk_alpha_pll_lucid_5lpe_ops, > > + }, > > + }, > > +}; > > + > > +static const struct parent_map gpu_cc_parent_map_0[] = { > > + { P_BI_TCXO, 0 }, > > + { P_GPU_CC_PLL0_OUT_MAIN, 1 }, > > + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, > > + { P_GPLL0_OUT_MAIN, 5 }, > > + { P_GPLL0_OUT_MAIN_DIV, 6 }, > > +}; > > + > > +static const struct clk_parent_data gpu_cc_parent_data_0[] = { > > + gpu_cc_parent, > > + { .hw = &gpu_cc_pll0.clkr.hw }, > > + { .hw = &gpu_cc_pll1.clkr.hw }, > > + { .fw_name = "gcc_gpu_gpll0_clk_src" }, > > + { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, > > +}; > > + > > +static const struct parent_map gpu_cc_parent_map_1[] = { > > + { P_BI_TCXO, 0 }, > > + { P_GPU_CC_PLL1_OUT_MAIN, 3 }, > > + { P_GPLL0_OUT_MAIN, 5 }, > > + { P_GPLL0_OUT_MAIN_DIV, 6 }, > > +}; > > + > > +static const struct clk_parent_data gpu_cc_parent_data_1[] = { > > + gpu_cc_parent, > > + { .hw = &gpu_cc_pll1.clkr.hw }, > > + { .fw_name = "gcc_gpu_gpll0_clk_src" }, > > + { .fw_name = "gcc_gpu_gpll0_div_clk_src" }, > > +}; > > + > > +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { > > + F(19200000, P_BI_TCXO, 1, 0, 0), > > + F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), > > + F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), > > + { } > > +}; > > + > > +static struct clk_rcg2 gpu_cc_gmu_clk_src = { > > + .cmd_rcgr = 0x1120, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = gpu_cc_parent_map_0, > > + .freq_tbl = ftbl_gpu_cc_gmu_clk_src, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_gmu_clk_src", > > + .parent_data = gpu_cc_parent_data_0, > > + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_0), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_rcg2_ops, > > + }, > > +}; > > + > > +static const struct freq_tbl ftbl_gpu_cc_hub_clk_src[] = { > > + F(150000000, P_GPLL0_OUT_MAIN_DIV, 2, 0, 0), > > + F(240000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0), > > + F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0), > > + { } > > +}; > > + > > +static struct clk_rcg2 gpu_cc_hub_clk_src = { > > + .cmd_rcgr = 0x117c, > > + .mnd_width = 0, > > + .hid_width = 5, > > + .parent_map = gpu_cc_parent_map_1, > > + .freq_tbl = ftbl_gpu_cc_hub_clk_src, > > + .clkr.hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_hub_clk_src", > > + .parent_data = gpu_cc_parent_data_1, > > + .num_parents = ARRAY_SIZE(gpu_cc_parent_data_1), > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_rcg2_ops, > > + }, > > +}; > > + > > +static struct clk_regmap_div gpu_cc_hub_ahb_div_clk_src = { > > + .reg = 0x11c0, > > + .shift = 0, > > + .width = 4, > > + .clkr.hw.init = &(struct clk_init_data) { > > + .name = "gpu_cc_hub_ahb_div_clk_src", > > + .parent_hws = (const struct clk_hw*[]){ > > + &gpu_cc_hub_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_regmap_div_ro_ops, > > + }, > > +}; > > + > > +static struct clk_regmap_div gpu_cc_hub_cx_int_div_clk_src = { > > + .reg = 0x11bc, > > + .shift = 0, > > + .width = 4, > > + .clkr.hw.init = &(struct clk_init_data) { > > + .name = "gpu_cc_hub_cx_int_div_clk_src", > > + .parent_hws = (const struct clk_hw*[]){ > > + &gpu_cc_hub_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_regmap_div_ro_ops, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_ahb_clk = { > > + .halt_reg = 0x1078, > > + .halt_check = BRANCH_HALT_DELAY, > > + .clkr = { > > + .enable_reg = 0x1078, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_ahb_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cb_clk = { > > + .halt_reg = 0x1170, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x1170, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cb_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_crc_ahb_clk = { > > + .halt_reg = 0x107c, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x107c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_crc_ahb_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &gpu_cc_hub_ahb_div_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cx_apb_clk = { > > + .halt_reg = 0x1088, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x1088, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cx_apb_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cx_gmu_clk = { > > + .halt_reg = 0x1098, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x1098, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cx_gmu_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &gpu_cc_gmu_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_aon_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cx_qdss_at_clk = { > > + .halt_reg = 0x1080, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x1080, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cx_qdss_at_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cx_qdss_trig_clk = { > > + .halt_reg = 0x1094, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x1094, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cx_qdss_trig_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cx_qdss_tsctr_clk = { > > + .halt_reg = 0x1084, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x1084, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cx_qdss_tsctr_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cx_snoc_dvm_clk = { > > + .halt_reg = 0x108c, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x108c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cx_snoc_dvm_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cxo_aon_clk = { > > + .halt_reg = 0x1004, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x1004, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cxo_aon_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_cxo_clk = { > > + .halt_reg = 0x109c, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x109c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_cxo_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_freq_measure_clk = { > > + .halt_reg = 0x120c, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x120c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_freq_measure_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_gx_gmu_clk = { > > + .halt_reg = 0x1064, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x1064, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_gx_gmu_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &gpu_cc_gmu_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_gx_qdss_tsctr_clk = { > > + .halt_reg = 0x105c, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x105c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_gx_qdss_tsctr_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_gx_vsense_clk = { > > + .halt_reg = 0x1058, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x1058, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_gx_vsense_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_hlos1_vote_gpu_smmu_clk = { > > + .halt_reg = 0x5000, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x5000, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_hlos1_vote_gpu_smmu_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_hub_aon_clk = { > > + .halt_reg = 0x1178, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x1178, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_hub_aon_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &gpu_cc_hub_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_aon_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_hub_cx_int_clk = { > > + .halt_reg = 0x1204, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x1204, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_hub_cx_int_clk", > > + .parent_hws = (const struct clk_hw*[]){ > > + &gpu_cc_hub_cx_int_div_clk_src.clkr.hw, > > + }, > > + .num_parents = 1, > > + .flags = CLK_SET_RATE_PARENT, > > + .ops = &clk_branch2_aon_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_mnd1x_0_gfx3d_clk = { > > + .halt_reg = 0x802c, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x802c, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_mnd1x_0_gfx3d_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_mnd1x_1_gfx3d_clk = { > > + .halt_reg = 0x8030, > > + .halt_check = BRANCH_HALT, > > + .clkr = { > > + .enable_reg = 0x8030, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_mnd1x_1_gfx3d_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct clk_branch gpu_cc_sleep_clk = { > > + .halt_reg = 0x1090, > > + .halt_check = BRANCH_HALT_VOTED, > > + .clkr = { > > + .enable_reg = 0x1090, > > + .enable_mask = BIT(0), > > + .hw.init = &(struct clk_init_data){ > > + .name = "gpu_cc_sleep_clk", > > + .ops = &clk_branch2_ops, > > + }, > > + }, > > +}; > > + > > +static struct gdsc gpu_cx_gdsc = { > > + .gdscr = 0x106c, > > + .gds_hw_ctrl = 0x1540, > > + .pd = { > > + .name = "gpu_cx_gdsc", > > + }, > > + .pwrsts = PWRSTS_OFF_ON, > > + .flags = VOTABLE, > > +}; > > + > > +static struct gdsc gpu_gx_gdsc = { > > + .gdscr = 0x100c, > > + .clamp_io_ctrl = 0x1508, > > + .pd = { > > + .name = "gpu_gx_gdsc", > > + .power_on = gdsc_gx_do_nothing_enable, > > + }, > > + .pwrsts = PWRSTS_OFF_ON, > > + .flags = CLAMP_IO | AON_RESET | POLL_CFG_GDSCR, > > +}; > > + > > +static struct clk_regmap *gpu_cc_sm8350_clocks[] = { > > + [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr, > > + [GPU_CC_CB_CLK] = &gpu_cc_cb_clk.clkr, > > + [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr, > > + [GPU_CC_CX_APB_CLK] = &gpu_cc_cx_apb_clk.clkr, > > + [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr, > > + [GPU_CC_CX_QDSS_AT_CLK] = &gpu_cc_cx_qdss_at_clk.clkr, > > + [GPU_CC_CX_QDSS_TRIG_CLK] = &gpu_cc_cx_qdss_trig_clk.clkr, > > + [GPU_CC_CX_QDSS_TSCTR_CLK] = &gpu_cc_cx_qdss_tsctr_clk.clkr, > > + [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr, > > + [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr, > > + [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr, > > + [GPU_CC_FREQ_MEASURE_CLK] = &gpu_cc_freq_measure_clk.clkr, > > + [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr, > > + [GPU_CC_GX_GMU_CLK] = &gpu_cc_gx_gmu_clk.clkr, > > + [GPU_CC_GX_QDSS_TSCTR_CLK] = &gpu_cc_gx_qdss_tsctr_clk.clkr, > > + [GPU_CC_GX_VSENSE_CLK] = &gpu_cc_gx_vsense_clk.clkr, > > + [GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK] = &gpu_cc_hlos1_vote_gpu_smmu_clk.clkr, > > + [GPU_CC_HUB_AHB_DIV_CLK_SRC] = &gpu_cc_hub_ahb_div_clk_src.clkr, > > + [GPU_CC_HUB_AON_CLK] = &gpu_cc_hub_aon_clk.clkr, > > + [GPU_CC_HUB_CLK_SRC] = &gpu_cc_hub_clk_src.clkr, > > + [GPU_CC_HUB_CX_INT_CLK] = &gpu_cc_hub_cx_int_clk.clkr, > > + [GPU_CC_HUB_CX_INT_DIV_CLK_SRC] = &gpu_cc_hub_cx_int_div_clk_src.clkr, > > + [GPU_CC_MND1X_0_GFX3D_CLK] = &gpu_cc_mnd1x_0_gfx3d_clk.clkr, > > + [GPU_CC_MND1X_1_GFX3D_CLK] = &gpu_cc_mnd1x_1_gfx3d_clk.clkr, > > + [GPU_CC_PLL0] = &gpu_cc_pll0.clkr, > > + [GPU_CC_PLL1] = &gpu_cc_pll1.clkr, > > + [GPU_CC_SLEEP_CLK] = &gpu_cc_sleep_clk.clkr, > > +}; > > + > > +static const struct qcom_reset_map gpu_cc_sm8350_resets[] = { > > + [GPUCC_GPU_CC_ACD_BCR] = { 0x1160 }, > > + [GPUCC_GPU_CC_CB_BCR] = { 0x116c }, > > + [GPUCC_GPU_CC_CX_BCR] = { 0x1068 }, > > + [GPUCC_GPU_CC_FAST_HUB_BCR] = { 0x1174 }, > > + [GPUCC_GPU_CC_GFX3D_AON_BCR] = { 0x10a0 }, > > + [GPUCC_GPU_CC_GMU_BCR] = { 0x111c }, > > + [GPUCC_GPU_CC_GX_BCR] = { 0x1008 }, > > + [GPUCC_GPU_CC_XO_BCR] = { 0x1000 }, > > +}; > > + > > +static struct gdsc *gpu_cc_sm8350_gdscs[] = { > > + [GPU_CX_GDSC] = &gpu_cx_gdsc, > > + [GPU_GX_GDSC] = &gpu_gx_gdsc, > > +}; > > + > > +static const struct regmap_config gpu_cc_sm8350_regmap_config = { > > + .reg_bits = 32, > > + .reg_stride = 4, > > + .val_bits = 32, > > + .max_register = 0x8030, > > + .fast_io = true, > > +}; > > + > > +static const struct qcom_cc_desc gpu_cc_sm8350_desc = { > > + .config = &gpu_cc_sm8350_regmap_config, > > + .clks = gpu_cc_sm8350_clocks, > > + .num_clks = ARRAY_SIZE(gpu_cc_sm8350_clocks), > > + .resets = gpu_cc_sm8350_resets, > > + .num_resets = ARRAY_SIZE(gpu_cc_sm8350_resets), > > + .gdscs = gpu_cc_sm8350_gdscs, > > + .num_gdscs = ARRAY_SIZE(gpu_cc_sm8350_gdscs), > > +}; > > + > > +static int gpu_cc_sm8350_probe(struct platform_device *pdev) > > +{ > > + struct regmap *regmap; > > + > > + regmap = qcom_cc_map(pdev, &gpu_cc_sm8350_desc); > > + if (IS_ERR(regmap)) { > > + dev_err(&pdev->dev, "Failed to map gpu cc registers\n"); > > + return PTR_ERR(regmap); > > + } > > + > > + clk_lucid_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config); > > + clk_lucid_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); > > + > > + return qcom_cc_really_probe(pdev, &gpu_cc_sm8350_desc, regmap); > > +} > > + > > +static const struct of_device_id gpu_cc_sm8350_match_table[] = { > > + { .compatible = "qcom,sm8350-gpucc" }, > > + { } > > +}; > > +MODULE_DEVICE_TABLE(of, gpu_cc_sm8350_match_table); > > + > > +static struct platform_driver gpu_cc_sm8350_driver = { > > + .probe = gpu_cc_sm8350_probe, > > + .driver = { > > + .name = "sm8350-gpucc", > > + .of_match_table = gpu_cc_sm8350_match_table, > > + }, > > +}; > > + > > +static int __init gpu_cc_sm8350_init(void) > > +{ > > + return platform_driver_register(&gpu_cc_sm8350_driver); > > +} > > +subsys_initcall(gpu_cc_sm8350_init); > > + > > +static void __exit gpu_cc_sm8350_exit(void) > > +{ > > + platform_driver_unregister(&gpu_cc_sm8350_driver); > > +} > > +module_exit(gpu_cc_sm8350_exit); > > + > > +MODULE_DESCRIPTION("QTI GPU_CC SM8350 Driver"); > > +MODULE_LICENSE("GPL v2");
On Wed, 22 Jun 2022 at 12:22, Konrad Dybcio <konrad.dybcio@somainline.org> wrote: > > > > On 22.06.2022 01:34, Robert Foss wrote: > > From: Jonathan Marek <jonathan@marek.ca> > > > > Add support to the SM8350 display clock controller by extending the SM8250 > > display clock controller, which is almost identical but has some minor > > differences. > > > > Signed-off-by: Jonathan Marek <jonathan@marek.ca> > > Signed-off-by: Robert Foss <robert.foss@linaro.org> > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > > --- > > > > Changes since v1 > > - Remove comment - Dmitry > > > > Changes since v2 > > - Add my SoB - Bjorn > > - Remove CLK_ASSUME_ENABLED_WHEN_UNUSED flag > > > > Changes since v3 > > - Add kconfig dependency on SM_GCC_8350 - Konrad > > - Change hex to lowercase - Konrad > > - Split from dispcc-sm8250.c implementation > > - Switch from .fw_name to .index > > > > Changes since v4 > > - Hex to lowercase - Konrad > > - Remove bad match table entries - Konrad > > > > Changes since v5 > > - Reverted split from dispcc-sm8250 > > - Re-added tags from v3 > > > > > > drivers/clk/qcom/Kconfig | 4 +-- > > drivers/clk/qcom/dispcc-sm8250.c | 60 +++++++++++++++++++++++++++++++- > > 2 files changed, 61 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig > > index b11235c21952..4c3d1a548b7a 100644 > > --- a/drivers/clk/qcom/Kconfig > > +++ b/drivers/clk/qcom/Kconfig > > @@ -618,11 +618,11 @@ config SM_DISPCC_6125 > > splash screen > > > > config SM_DISPCC_8250 > > - tristate "SM8150 and SM8250 Display Clock Controller" > > + tristate "SM8150/SM8250/SM8350 Display Clock Controller" > > depends on SM_GCC_8150 || SM_GCC_8250 > || SM_GCC_8350 Ack > > > help > > Support for the display clock controller on Qualcomm Technologies, Inc > > - SM8150 and SM8250 devices. > > + SM8150/SM8250/SM8350 devices. > > Say Y if you want to support display devices and functionality such as > > splash screen. > > > > diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c > > index db9379634fb2..4e101d584115 100644 > > --- a/drivers/clk/qcom/dispcc-sm8250.c > > +++ b/drivers/clk/qcom/dispcc-sm8250.c > > @@ -43,6 +43,10 @@ static struct pll_vco vco_table[] = { > > { 249600000, 2000000000, 0 }, > > }; > > > > +static struct pll_vco lucid_5lpe_vco[] = { > > + { 249600000, 1750000000, 0 }, > > +}; > > + > > static struct alpha_pll_config disp_cc_pll0_config = { > > .l = 0x47, > > .alpha = 0xE000, > > @@ -1228,6 +1232,7 @@ static const struct of_device_id disp_cc_sm8250_match_table[] = { > > { .compatible = "qcom,sc8180x-dispcc" }, > > { .compatible = "qcom,sm8150-dispcc" }, > > { .compatible = "qcom,sm8250-dispcc" }, > > + { .compatible = "qcom,sm8350-dispcc" }, > > { } > > }; > > MODULE_DEVICE_TABLE(of, disp_cc_sm8250_match_table); > > @@ -1258,7 +1263,7 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) > > return PTR_ERR(regmap); > > } > > > > - /* note: trion == lucid, except for the prepare() op */ > > + /* Apply differences for SM8150 and SM8350 */ > I think both comments should stay, as the one you're adding doesn't explain the BUILD_BUG_ON() Ack > > > Konrad > > BUILD_BUG_ON(CLK_ALPHA_PLL_TYPE_TRION != CLK_ALPHA_PLL_TYPE_LUCID); > > if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-dispcc") || > > of_device_is_compatible(pdev->dev.of_node, "qcom,sm8150-dispcc")) { > > @@ -1270,6 +1275,59 @@ static int disp_cc_sm8250_probe(struct platform_device *pdev) > > disp_cc_pll1_config.config_ctl_hi1_val = 0x00000024; > > disp_cc_pll1_config.user_ctl_hi1_val = 0x000000D0; > > disp_cc_pll1_init.ops = &clk_alpha_pll_trion_ops; > > + } else if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8350-dispcc")) { > > + static struct clk_rcg2 * const rcgs[] = { > > + &disp_cc_mdss_byte0_clk_src, > > + &disp_cc_mdss_byte1_clk_src, > > + &disp_cc_mdss_dp_aux1_clk_src, > > + &disp_cc_mdss_dp_aux_clk_src, > > + &disp_cc_mdss_dp_link1_clk_src, > > + &disp_cc_mdss_dp_link_clk_src, > > + &disp_cc_mdss_dp_pixel1_clk_src, > > + &disp_cc_mdss_dp_pixel2_clk_src, > > + &disp_cc_mdss_dp_pixel_clk_src, > > + &disp_cc_mdss_esc0_clk_src, > > + &disp_cc_mdss_mdp_clk_src, > > + &disp_cc_mdss_pclk0_clk_src, > > + &disp_cc_mdss_pclk1_clk_src, > > + &disp_cc_mdss_rot_clk_src, > > + &disp_cc_mdss_vsync_clk_src, > > + }; > > + static struct clk_regmap_div * const divs[] = { > > + &disp_cc_mdss_byte0_div_clk_src, > > + &disp_cc_mdss_byte1_div_clk_src, > > + &disp_cc_mdss_dp_link1_div_clk_src, > > + &disp_cc_mdss_dp_link_div_clk_src, > > + }; > > + unsigned int i; > > + static bool offset_applied; > > + > > + /* only apply the offsets once (in case of deferred probe) */ > > + if (!offset_applied) { > > + for (i = 0; i < ARRAY_SIZE(rcgs); i++) > > + rcgs[i]->cmd_rcgr -= 4; > > + > > + for (i = 0; i < ARRAY_SIZE(divs); i++) { > > + divs[i]->reg -= 4; > > + divs[i]->width = 4; > > + } > > + > > + disp_cc_mdss_ahb_clk.halt_reg -= 4; > > + disp_cc_mdss_ahb_clk.clkr.enable_reg -= 4; > > + > > + offset_applied = true; > > + } > > + > > + disp_cc_mdss_ahb_clk_src.cmd_rcgr = 0x22a0; > > + > > + disp_cc_pll0_config.config_ctl_hi1_val = 0x2a9a699c; > > + disp_cc_pll0_config.test_ctl_hi1_val = 0x01800000; > > + disp_cc_pll0_init.ops = &clk_alpha_pll_lucid_5lpe_ops; > > + disp_cc_pll0.vco_table = lucid_5lpe_vco; > > + disp_cc_pll1_config.config_ctl_hi1_val = 0x2a9a699c; > > + disp_cc_pll1_config.test_ctl_hi1_val = 0x01800000; > > + disp_cc_pll1_init.ops = &clk_alpha_pll_lucid_5lpe_ops; > > + disp_cc_pll1.vco_table = lucid_5lpe_vco; > > } > > > > clk_lucid_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);