| Message ID | 20220523060056.24396-1-rex-bc.chen@mediatek.com |
|---|---|
| Headers | show |
| Series | Cleanup MediaTek clk reset drivers and support SoCs | expand |
Il 23/05/22 08:00, Rex-BC Chen ha scritto: > The infra_ao reset is needed for MT8186. > - Add mtk_clk_rst_desc for MT8186. > - Add register reset controller function for MT8186 infra_ao. > - Add infra_ao_idx_map for MT8186. > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> For the code: Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
On Mon, 2022-05-23 at 14:00 +0800, Rex-BC Chen wrote: > We will use mediatek clock reset as infracfg_ao reset instead of > ti-syscon. To support this, remove property of ti reset and add > property of #reset-cells for mediatek clock reset. > > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com> > --- > arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 ++------------- > 1 file changed, 2 insertions(+), 13 deletions(-) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > index b57e620c2c72..db16eba9d475 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi > @@ -10,7 +10,6 @@ > #include <dt-bindings/interrupt-controller/irq.h> > #include <dt-bindings/phy/phy.h> > #include <dt-bindings/pinctrl/mt8195-pinfunc.h> > -#include <dt-bindings/reset/ti-syscon.h> > > / { > compatible = "mediatek,mt8195"; > @@ -292,20 +291,10 @@ > }; > > infracfg_ao: syscon@10001000 { > - compatible = "mediatek,mt8195-infracfg_ao", > "syscon", "simple-mfd"; > + compatible = "mediatek,mt8195-infracfg_ao", > "syscon"; > reg = <0 0x10001000 0 0x1000>; > #clock-cells = <1>; > - > - infracfg_rst: reset-controller { > - compatible = "ti,syscon-reset"; > - #reset-cells = <1>; > - ti,reset-bits = < > - 0x140 18 0x144 18 0 0 > (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */ > - 0x120 0 0x124 0 0 0 > (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ > - 0x730 10 0x734 10 0 0 > (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */ > - 0x150 5 0x154 5 0 0 > (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */ > - >; > - }; > + #reset-cells = <1>; > }; > > pericfg: syscon@10003000 { > -- > 2.18.0 > Hello Matthias, driver part is accepted by Setphen[1]. dts part is also reviewed. Is these dts parts ok for you? (including patch 15 and 16) Or should I send another series for dts part? Thanks! [1]: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git/log/?h=clk-next BRs, Bo-Chen
In this series, we cleanup MediaTek clock reset drivers in clk/mediatek folder. MediaTek clock reset driver is used to provide reset control of modules controlled in clk, like infra_ao. Changes for v8: 1. Use 'enum mtk_reset_version' to replace u8 in patch 5 and 6. 2. Use lowercase '0xc' in patch 7. 3. Drop "simple-mfd" in patch 16 because it's for original reset controller. 4. v8 is based on linux-next next-20220520 and Chen-Yu's series[1]. Changes for v7: 1. v7 is based on linux-next next-20220519 and Chen-Yu's series[1]. 2. Add support for MT8186. [1]: https://patchwork.kernel.org/project/linux-mediatek/list/?series=643003 Changes for v6: 1. Add a new patch to support inuput argument index mode. 2. Revise definition in reset.h to index. Rex-BC Chen (19): clk: mediatek: reset: Add reset.h clk: mediatek: reset: Fix written reset bit offset clk: mediatek: reset: Refine and reorder functions in reset.c clk: mediatek: reset: Extract common drivers to update function clk: mediatek: reset: Merge and revise reset register function clk: mediatek: reset: Revise structure to control reset register clk: mediatek: reset: Support nonsequence base offsets of reset registers clk: mediatek: reset: Support inuput argument index mode clk: mediatek: reset: Change return type for clock reset register function clk: mediatek: reset: Add new register reset function with device clk: mediatek: reset: Add reset support for simple probe dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195 dt-bindings: reset: mediatek: Add infra_ao reset index for MT8192/MT8195 clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195 arm64: dts: mediatek: Add infra #reset-cells property for MT8192 arm64: dts: mediatek: Add infra #reset-cells property for MT8195 dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186 dt-bindings: arm: mediatek: Add #reset-cells property for MT8186 clk: mediatek: reset: Add infra_ao reset support for MT8186 .../mediatek/mediatek,mt8186-sys-clock.yaml | 3 + .../mediatek/mediatek,mt8192-sys-clock.yaml | 3 + .../mediatek/mediatek,mt8195-sys-clock.yaml | 3 + arch/arm64/boot/dts/mediatek/mt8192.dtsi | 1 + arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +- drivers/clk/mediatek/clk-mt2701-eth.c | 10 +- drivers/clk/mediatek/clk-mt2701-g3d.c | 10 +- drivers/clk/mediatek/clk-mt2701-hif.c | 10 +- drivers/clk/mediatek/clk-mt2701.c | 22 +- drivers/clk/mediatek/clk-mt2712.c | 22 +- drivers/clk/mediatek/clk-mt7622-eth.c | 10 +- drivers/clk/mediatek/clk-mt7622-hif.c | 12 +- drivers/clk/mediatek/clk-mt7622.c | 22 +- drivers/clk/mediatek/clk-mt7629-eth.c | 10 +- drivers/clk/mediatek/clk-mt7629-hif.c | 12 +- drivers/clk/mediatek/clk-mt8135.c | 22 +- drivers/clk/mediatek/clk-mt8173.c | 22 +- drivers/clk/mediatek/clk-mt8183.c | 18 +- drivers/clk/mediatek/clk-mt8186-infra_ao.c | 23 ++ drivers/clk/mediatek/clk-mt8192.c | 29 +++ drivers/clk/mediatek/clk-mt8195-infra_ao.c | 24 +++ drivers/clk/mediatek/clk-mtk.c | 7 + drivers/clk/mediatek/clk-mtk.h | 9 +- drivers/clk/mediatek/reset.c | 198 +++++++++++++----- drivers/clk/mediatek/reset.h | 82 ++++++++ include/dt-bindings/reset/mt8186-resets.h | 5 + include/dt-bindings/reset/mt8192-resets.h | 8 + include/dt-bindings/reset/mt8195-resets.h | 6 + 28 files changed, 523 insertions(+), 95 deletions(-) create mode 100644 drivers/clk/mediatek/reset.h