| Message ID | 20220610105522.13449-1-rex-bc.chen@mediatek.com |
|---|---|
| Headers | show |
| Series | drm/mediatek: Add MT8195 DisplayPort driver | expand |
Hi, Bo-Chen: On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@mediatek.com> > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- [snip] > + > +static int mtk_dp_train_flow(struct mtk_dp *mtk_dp, u8 > target_link_rate, > + u8 target_lane_count) > +{ > + u8 lane_adjust[2] = {}; > + bool pass_tps1 = false; > + bool pass_tps2_3 = false; > + int train_retries; > + int status_control; > + int iteration_count; > + int ret; > + u8 prev_lane_adjust; > + > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LINK_BW_SET, > target_link_rate); > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET, > + target_lane_count | > DP_LANE_COUNT_ENHANCED_FRAME_EN); > + > + if (mtk_dp->train_info.sink_ssc) > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_DOWNSPREAD_CTRL, > + DP_SPREAD_AMP_0_5); > + > + train_retries = 0; > + status_control = 0; > + iteration_count = 1; > + prev_lane_adjust = 0xFF; > + > + mtk_dp_set_lanes(mtk_dp, target_lane_count / 2); > + ret = mtk_dp_phy_configure(mtk_dp, target_link_rate, > target_lane_count); > + if (ret) > + return -EINVAL; > + > + dev_dbg(mtk_dp->dev, > + "Link train target_link_rate = 0x%x, target_lane_count > = 0x%x\n", > + target_link_rate, target_lane_count); > + > + do { > + train_retries++; > + if (!mtk_dp->train_info.cable_plugged_in || > + mtk_dp->train_info.irq_sta.hpd_disconnect) { In mtk_dp_hpd_isr_handler(), train_info.irq_sta.hpd_disconnect would finally be set to false, so you need not to check it here. So remove it here. > + return -ENODEV; > + } > + > + if (mtk_dp->train_state < MTK_DP_TRAIN_STATE_TRAINING) > + return -EAGAIN; > + > + if (!pass_tps1) { > + ret = mtk_dp_train_tps_1(mtk_dp, > target_lane_count, > + &iteration_count, > lane_adjust, > + &status_control, > + &prev_lane_adjust); > + if (!ret) { > + pass_tps1 = true; > + train_retries = 0; > + } else if (ret == -EINVAL) { > + break; > + } > + } else { > + ret = mtk_dp_train_tps_2_3(mtk_dp, > target_link_rate, > + target_lane_count, > + &iteration_count, > + lane_adjust, > &status_control, > + &prev_lane_adjust); > + if (!ret) { > + pass_tps2_3 = true; > + break; > + } else if (ret == -EINVAL) { > + break; > + } > + } > + > + drm_dp_dpcd_read(&mtk_dp->aux, > DP_ADJUST_REQUEST_LANE0_1, > + lane_adjust, sizeof(lane_adjust)); > + mtk_dp_train_update_swing_pre(mtk_dp, > target_lane_count, > + lane_adjust); > + } while (train_retries < MTK_DP_TRAIN_RETRY_LIMIT && > + iteration_count < MTK_DP_TRAIN_MAX_ITERATIONS); > + > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET, > + DP_TRAINING_PATTERN_DISABLE); > + ret = mtk_dp_train_set_pattern(mtk_dp, 0); > + if (ret) > + return -EINVAL; > + > + if (!pass_tps2_3) > + return -ETIMEDOUT; > + > + mtk_dp->train_info.link_rate = target_link_rate; > + mtk_dp->train_info.lane_count = target_lane_count; > + > + mtk_dp_training_set_scramble(mtk_dp, true); > + > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET, > + target_lane_count | > + DP_LANE_COUNT_ENHANCED_FRAME_EN); > + mtk_dp_set_enhanced_frame_mode(mtk_dp, true); > + > + return ret; > +} > + [snip] > + > +/* > + * We need to handle HPD signal in eDP even though eDP is a always > connected > + * device. Besides connected status, there is another feature for > HPD signal - > + * HPD pulse: it presents an IRQ from sink devices to source devices > (Refer to > + * 5.1.4 of DP1.4 spec). > + */ > +static irqreturn_t mtk_dp_hpd_isr_handler(struct mtk_dp *mtk_dp) > +{ > + bool connected; > + u32 irq_status = mtk_dp_swirq_get_clear(mtk_dp) | > + mtk_dp_hwirq_get_clear(mtk_dp); > + struct mtk_dp_train_info *train_info = &mtk_dp->train_info; > + > + if (irq_status & MTK_DP_HPD_INTERRUPT) > + train_info->irq_sta.hpd_inerrupt = true; > + if (irq_status & MTK_DP_HPD_CONNECT) > + train_info->irq_sta.hpd_connect = true; > + if (irq_status & MTK_DP_HPD_DISCONNECT) > + train_info->irq_sta.hpd_disconnect = true; > + train_info->irq_sta.hpd_connect is used only in this function, so let hpd_connect to be local variable. > + if (!irq_status) > + return IRQ_HANDLED; > + > + connected = mtk_dp_plug_state(mtk_dp); > + if (connected || !train_info->cable_plugged_in) > + train_info->irq_sta.hpd_disconnect = false; > + else if (!connected || train_info->cable_plugged_in) > + train_info->irq_sta.hpd_connect = false; > + > + if (!(train_info->irq_sta.hpd_connect || > + train_info->irq_sta.hpd_disconnect)) > + return IRQ_WAKE_THREAD; > + > + if (train_info->irq_sta.hpd_connect) { > + train_info->irq_sta.hpd_connect = false; > + train_info->cable_plugged_in = true; > + } else { > + train_info->irq_sta.hpd_disconnect = false; > + train_info->cable_plugged_in = false; > + mtk_dp->train_state = MTK_DP_TRAIN_STATE_TRAINING; > + } > + train_info->cable_state_change = true; > + > + return IRQ_WAKE_THREAD; > +} > + [snip] > + > +static ssize_t mtk_dp_aux_transfer(struct drm_dp_aux *mtk_aux, > + struct drm_dp_aux_msg *msg) > +{ > + struct mtk_dp *mtk_dp; > + bool is_read; > + u8 request; > + size_t accessed_bytes = 0; > + int ret = 0; > + > + mtk_dp = container_of(mtk_aux, struct mtk_dp, aux); > + > + if (!mtk_dp->train_info.cable_plugged_in || > + mtk_dp->train_info.irq_sta.hpd_disconnect) { In mtk_dp_hpd_isr_handler(), train_info.irq_sta.hpd_disconnect would finally be set to false, so you need not to check it here. So remove it here. Regards, CK > + ret = -EAGAIN; > + goto err; > + } > + > + switch (msg->request) { > + case DP_AUX_I2C_MOT: > + case DP_AUX_I2C_WRITE: > + case DP_AUX_NATIVE_WRITE: > + case DP_AUX_I2C_WRITE_STATUS_UPDATE: > + case DP_AUX_I2C_WRITE_STATUS_UPDATE | DP_AUX_I2C_MOT: > + request = msg->request & > ~DP_AUX_I2C_WRITE_STATUS_UPDATE; > + is_read = false; > + break; > + case DP_AUX_I2C_READ: > + case DP_AUX_NATIVE_READ: > + case DP_AUX_I2C_READ | DP_AUX_I2C_MOT: > + request = msg->request; > + is_read = true; > + break; > + default: > + drm_err(mtk_aux->drm_dev, "invalid aux cmd = %d\n", > + msg->request); > + ret = -EINVAL; > + goto err; > + } > + > + if (msg->size == 0) { > + ret = mtk_dp_aux_do_transfer(mtk_dp, is_read, request, > + msg->address + > accessed_bytes, > + msg->buffer + > accessed_bytes, 0); > + } else { > + while (accessed_bytes < msg->size) { > + size_t to_access = > + min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES, > + msg->size - accessed_bytes); > + > + ret = mtk_dp_aux_do_transfer(mtk_dp, is_read, > request, > + msg->address + > accessed_bytes, > + msg->buffer + > accessed_bytes, > + to_access); > + > + if (ret) { > + drm_info(mtk_dp->drm_dev, > + "Failed to do AUX transfer: > %d\n", ret); > + break; > + } > + accessed_bytes += to_access; > + } > + } > +err: > + if (ret) { > + msg->reply = DP_AUX_NATIVE_REPLY_NACK | > DP_AUX_I2C_REPLY_NACK; > + return ret; > + } > + > + msg->reply = DP_AUX_NATIVE_REPLY_ACK | DP_AUX_I2C_REPLY_ACK; > + return msg->size; > +} > +
Hi, Bo-Chen: On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@mediatek.com> > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- [snip] > + > +static int mtk_dp_parse_capabilities(struct mtk_dp *mtk_dp) > +{ > + u8 val; > + struct mtk_dp_train_info *train_info = &mtk_dp->train_info; > + > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, > DP_SET_POWER_D0); > + usleep_range(2000, 5000); > + > + drm_dp_read_dpcd_caps(&mtk_dp->aux, mtk_dp->rx_cap); > + > + mtk_dp->rx_cap[DP_TRAINING_AUX_RD_INTERVAL] &= > DP_TRAINING_AUX_RD_MASK; > + > + train_info->link_rate = min_t(int, mtk_dp->max_linkrate, > + mtk_dp->rx_cap[mtk_dp- > >max_linkrate]); > + train_info->lane_count = min_t(int, mtk_dp->max_lanes, > + drm_dp_max_lane_count(mtk_dp- > >rx_cap)); > + > + train_info->tps3 = drm_dp_tps3_supported(mtk_dp->rx_cap); > + train_info->tps4 = drm_dp_tps4_supported(mtk_dp->rx_cap); > + > + train_info->sink_ssc = !!(mtk_dp->rx_cap[DP_MAX_DOWNSPREAD] & > + DP_MAX_DOWNSPREAD_0_5); I think this is redundant because next statement would set sink_scc to false. Regards, CK > + > + train_info->sink_ssc = false; > + > + drm_dp_dpcd_readb(&mtk_dp->aux, DP_MSTM_CAP, &val); > + if (val & DP_MST_CAP) { > + /* Clear DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 */ > + drm_dp_dpcd_readb(&mtk_dp->aux, > + DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0, > &val); > + if (val) > + drm_dp_dpcd_writeb(&mtk_dp->aux, > + DP_DEVICE_SERVICE_IRQ_VECTOR > _ESI0, > + val); > + } > + > + return 0; > +}
Hi, Bo-Chen: On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@mediatek.com> > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- [snip] > + > +static int mtk_dp_train_flow(struct mtk_dp *mtk_dp, u8 > target_link_rate, > + u8 target_lane_count) > +{ > + u8 lane_adjust[2] = {}; > + bool pass_tps1 = false; > + bool pass_tps2_3 = false; > + int train_retries; > + int status_control; > + int iteration_count; > + int ret; > + u8 prev_lane_adjust; > + > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LINK_BW_SET, > target_link_rate); > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET, > + target_lane_count | > DP_LANE_COUNT_ENHANCED_FRAME_EN); > + > + if (mtk_dp->train_info.sink_ssc) > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_DOWNSPREAD_CTRL, > + DP_SPREAD_AMP_0_5); > + > + train_retries = 0; > + status_control = 0; > + iteration_count = 1; > + prev_lane_adjust = 0xFF; > + > + mtk_dp_set_lanes(mtk_dp, target_lane_count / 2); > + ret = mtk_dp_phy_configure(mtk_dp, target_link_rate, > target_lane_count); > + if (ret) > + return -EINVAL; > + > + dev_dbg(mtk_dp->dev, > + "Link train target_link_rate = 0x%x, target_lane_count > = 0x%x\n", > + target_link_rate, target_lane_count); > + > + do { > + train_retries++; > + if (!mtk_dp->train_info.cable_plugged_in || > + mtk_dp->train_info.irq_sta.hpd_disconnect) { > + return -ENODEV; > + } > + > + if (mtk_dp->train_state < MTK_DP_TRAIN_STATE_TRAINING) This checking would never be true, so remove it. > + return -EAGAIN; > + > + if (!pass_tps1) { > + ret = mtk_dp_train_tps_1(mtk_dp, > target_lane_count, > + &iteration_count, > lane_adjust, > + &status_control, > + &prev_lane_adjust); > + if (!ret) { > + pass_tps1 = true; > + train_retries = 0; > + } else if (ret == -EINVAL) { > + break; > + } > + } else { > + ret = mtk_dp_train_tps_2_3(mtk_dp, > target_link_rate, > + target_lane_count, > + &iteration_count, > + lane_adjust, > &status_control, > + &prev_lane_adjust); > + if (!ret) { > + pass_tps2_3 = true; > + break; > + } else if (ret == -EINVAL) { > + break; > + } > + } > + > + drm_dp_dpcd_read(&mtk_dp->aux, > DP_ADJUST_REQUEST_LANE0_1, > + lane_adjust, sizeof(lane_adjust)); > + mtk_dp_train_update_swing_pre(mtk_dp, > target_lane_count, > + lane_adjust); > + } while (train_retries < MTK_DP_TRAIN_RETRY_LIMIT && > + iteration_count < MTK_DP_TRAIN_MAX_ITERATIONS); mtk_dp_train_tps_1() & mtk_dp_train_tps_2_3() would only be called once and never be called twice, so remove this loop. Regards, CK > + > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET, > + DP_TRAINING_PATTERN_DISABLE); > + ret = mtk_dp_train_set_pattern(mtk_dp, 0); > + if (ret) > + return -EINVAL; > + > + if (!pass_tps2_3) > + return -ETIMEDOUT; > + > + mtk_dp->train_info.link_rate = target_link_rate; > + mtk_dp->train_info.lane_count = target_lane_count; > + > + mtk_dp_training_set_scramble(mtk_dp, true); > + > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET, > + target_lane_count | > + DP_LANE_COUNT_ENHANCED_FRAME_EN); > + mtk_dp_set_enhanced_frame_mode(mtk_dp, true); > + > + return ret; > +}
Hi, Bo-Chen: On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@mediatek.com> > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- [snip] > + > +static int mtk_dp_train_set_pattern(struct mtk_dp *mtk_dp, int > pattern) > +{ > + if (pattern < 0 || pattern > 4) { The caller would pass pattern from 0 to 4, so this checking is redundant. Remove it and this function would always return true, so let this function be void. Regards, CK > + drm_err(mtk_dp->drm_dev, > + "Implementation error, no such pattern %d\n", > pattern); > + return -EINVAL; > + } > + > + /* TPS1 */ > + if (pattern == 1) > + mtk_dp_set_idle_pattern(mtk_dp, false); > + > + mtk_dp_update_bits(mtk_dp, > + MTK_DP_TRANS_P0_3400, > + pattern ? > + BIT(pattern - 1) << > PATTERN1_EN_DP_TRANS_P0_SHIFT : > + 0, > + PATTERN1_EN_DP_TRANS_P0_MASK | > + PATTERN2_EN_DP_TRANS_P0_MASK | > + PATTERN3_EN_DP_TRANS_P0_MASK | > + PATTERN4_EN_DP_TRANS_P0_MASK); > + return 0; > +}
Hi, Bo-Chen: On Wed, 2022-06-15 at 13:50 +0800, CK Hu wrote: > Hi, Bo-Chen: > > On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > > From: Markus Schneider-Pargmann <msp@baylibre.com> > > > > This patch adds a embedded displayport driver for the MediaTek > > mt8195 > > SoC. > > > > It supports the MT8195, the embedded DisplayPort units. It offers > > DisplayPort 1.4 with up to 4 lanes. > > > > The driver creates a child device for the phy. The child device > > will > > never exist without the parent being active. As they are sharing a > > register range, the parent passes a regmap pointer to the child so > > that > > both can work with the same register range. The phy driver sets > > device > > data that is read by the parent to get the phy device that can be > > used > > to control the phy properties. > > > > This driver is based on an initial version by > > Jitao shi <jitao.shi@mediatek.com> > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > > --- > > [snip] > > > + > > +static int mtk_dp_train_flow(struct mtk_dp *mtk_dp, u8 > > target_link_rate, > > + u8 target_lane_count) > > +{ > > + u8 lane_adjust[2] = {}; > > + bool pass_tps1 = false; > > + bool pass_tps2_3 = false; > > + int train_retries; > > + int status_control; > > + int iteration_count; > > + int ret; > > + u8 prev_lane_adjust; > > + > > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LINK_BW_SET, > > target_link_rate); > > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET, > > + target_lane_count | > > DP_LANE_COUNT_ENHANCED_FRAME_EN); > > + > > + if (mtk_dp->train_info.sink_ssc) > > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_DOWNSPREAD_CTRL, > > + DP_SPREAD_AMP_0_5); > > + > > + train_retries = 0; > > + status_control = 0; > > + iteration_count = 1; > > + prev_lane_adjust = 0xFF; > > + > > + mtk_dp_set_lanes(mtk_dp, target_lane_count / 2); > > + ret = mtk_dp_phy_configure(mtk_dp, target_link_rate, > > target_lane_count); > > + if (ret) > > + return -EINVAL; > > + > > + dev_dbg(mtk_dp->dev, > > + "Link train target_link_rate = 0x%x, target_lane_count > > = 0x%x\n", > > + target_link_rate, target_lane_count); > > + > > + do { > > + train_retries++; > > + if (!mtk_dp->train_info.cable_plugged_in || > > + mtk_dp->train_info.irq_sta.hpd_disconnect) { > > + return -ENODEV; > > + } > > + > > + if (mtk_dp->train_state < MTK_DP_TRAIN_STATE_TRAINING) > > This checking would never be true, so remove it. > > > + return -EAGAIN; > > + > > + if (!pass_tps1) { > > + ret = mtk_dp_train_tps_1(mtk_dp, > > target_lane_count, > > + &iteration_count, > > lane_adjust, > > + &status_control, > > + &prev_lane_adjust); > > + if (!ret) { > > + pass_tps1 = true; > > + train_retries = 0; > > + } else if (ret == -EINVAL) { > > + break; > > + } > > + } else { > > + ret = mtk_dp_train_tps_2_3(mtk_dp, > > target_link_rate, > > + target_lane_count, > > + &iteration_count, > > + lane_adjust, > > &status_control, > > + &prev_lane_adjust); > > + if (!ret) { > > + pass_tps2_3 = true; > > + break; > > + } else if (ret == -EINVAL) { > > + break; > > + } > > + } > > + > > + drm_dp_dpcd_read(&mtk_dp->aux, > > DP_ADJUST_REQUEST_LANE0_1, > > + lane_adjust, sizeof(lane_adjust)); > > + mtk_dp_train_update_swing_pre(mtk_dp, > > target_lane_count, > > + lane_adjust); > > + } while (train_retries < MTK_DP_TRAIN_RETRY_LIMIT && > > + iteration_count < MTK_DP_TRAIN_MAX_ITERATIONS); > > mtk_dp_train_tps_1() & mtk_dp_train_tps_2_3() would only be called > once > and never be called twice, so remove this loop. Sorry, mtk_dp_train_tps_1() & mtk_dp_train_tps_2_3() may return -EAGAIN, so keep this loop. > > Regards, > CK > > > + > > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET, > > + DP_TRAINING_PATTERN_DISABLE); > > + ret = mtk_dp_train_set_pattern(mtk_dp, 0); > > + if (ret) > > + return -EINVAL; > > + > > + if (!pass_tps2_3) > > + return -ETIMEDOUT; > > + > > + mtk_dp->train_info.link_rate = target_link_rate; > > + mtk_dp->train_info.lane_count = target_lane_count; > > + > > + mtk_dp_training_set_scramble(mtk_dp, true); > > + > > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET, > > + target_lane_count | > > + DP_LANE_COUNT_ENHANCED_FRAME_EN); > > + mtk_dp_set_enhanced_frame_mode(mtk_dp, true); > > + > > + return ret; > > +}
Hi, Bo-Chen: On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@mediatek.com> > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- [snip] > + > +static int mtk_dp_train_start(struct mtk_dp *mtk_dp) > +{ > + int ret = 0; > + u8 lane_count; > + u8 link_rate; > + u8 train_limit; > + u8 max_link_rate; > + > + link_rate = mtk_dp->rx_cap[1]; > + lane_count = mtk_dp->rx_cap[2] & 0x1F; > + > + mtk_dp->train_info.link_rate = min(mtk_dp->max_linkrate, > link_rate); > + mtk_dp->train_info.lane_count = min(mtk_dp->max_lanes, > lane_count); > + link_rate = mtk_dp->train_info.link_rate; > + lane_count = mtk_dp->train_info.lane_count; > + > + switch (link_rate) { > + case MTK_DP_LINKRATE_RBR: > + case MTK_DP_LINKRATE_HBR: > + case MTK_DP_LINKRATE_HBR2: > + case MTK_DP_LINKRATE_HBR25: > + case MTK_DP_LINKRATE_HBR3: > + break; > + default: > + mtk_dp->train_info.link_rate = MTK_DP_LINKRATE_HBR3; > + break; > + }; > + > + max_link_rate = link_rate; > + for (train_limit = 6; train_limit > 0; train_limit--) { > + mtk_dp->train_info.cr_done = false; > + mtk_dp->train_info.eq_done = false; > + > + mtk_dp_train_change_mode(mtk_dp); > + ret = mtk_dp_train_flow(mtk_dp, link_rate, lane_count); > + if (ret) > + return ret; > + > + if (!mtk_dp->train_info.cr_done) { When mtk_dp_train_flow() return 0, it imply train_info.cr_done is true, isn't it? > + switch (link_rate) { > + case MTK_DP_LINKRATE_RBR: > + lane_count = lane_count / 2; > + link_rate = max_link_rate; > + if (lane_count == 0) > + return -EIO; > + break; > + case MTK_DP_LINKRATE_HBR: > + link_rate = MTK_DP_LINKRATE_RBR; > + break; > + case MTK_DP_LINKRATE_HBR2: > + link_rate = MTK_DP_LINKRATE_HBR; > + break; > + case MTK_DP_LINKRATE_HBR3: > + link_rate = MTK_DP_LINKRATE_HBR2; > + break; > + default: > + return -EINVAL; > + }; > + } else if (!mtk_dp->train_info.eq_done) { When mtk_dp_train_flow() return 0, it imply train_info.eq_done is true, isn't it? Regards, CK > + if (lane_count == 0) > + return -EIO; > + > + lane_count /= 2; > + } else { > + break; > + } > + } > + > + if (train_limit == 0) > + return -ETIMEDOUT; > + > + return 0; > +}
On Wed, 2022-06-15 at 10:58 +0800, CK Hu wrote: > Hi, Bo-Chen: > > On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > > From: Markus Schneider-Pargmann <msp@baylibre.com> > > > > This patch adds a embedded displayport driver for the MediaTek > > mt8195 > > SoC. > > > > It supports the MT8195, the embedded DisplayPort units. It offers > > DisplayPort 1.4 with up to 4 lanes. > > > > The driver creates a child device for the phy. The child device > > will > > never exist without the parent being active. As they are sharing a > > register range, the parent passes a regmap pointer to the child so > > that > > both can work with the same register range. The phy driver sets > > device > > data that is read by the parent to get the phy device that can be > > used > > to control the phy properties. > > > > This driver is based on an initial version by > > Jitao shi <jitao.shi@mediatek.com> > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > > --- > > [snip] > > > + > > +static int mtk_dp_train_flow(struct mtk_dp *mtk_dp, u8 > > target_link_rate, > > + u8 target_lane_count) > > +{ > > + u8 lane_adjust[2] = {}; > > + bool pass_tps1 = false; > > + bool pass_tps2_3 = false; > > + int train_retries; > > + int status_control; > > + int iteration_count; > > + int ret; > > + u8 prev_lane_adjust; > > + > > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LINK_BW_SET, > > target_link_rate); > > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET, > > + target_lane_count | > > DP_LANE_COUNT_ENHANCED_FRAME_EN); > > + > > + if (mtk_dp->train_info.sink_ssc) > > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_DOWNSPREAD_CTRL, > > + DP_SPREAD_AMP_0_5); > > + > > + train_retries = 0; > > + status_control = 0; > > + iteration_count = 1; > > + prev_lane_adjust = 0xFF; > > + > > + mtk_dp_set_lanes(mtk_dp, target_lane_count / 2); > > + ret = mtk_dp_phy_configure(mtk_dp, target_link_rate, > > target_lane_count); > > + if (ret) > > + return -EINVAL; > > + > > + dev_dbg(mtk_dp->dev, > > + "Link train target_link_rate = 0x%x, target_lane_count > > = 0x%x\n", > > + target_link_rate, target_lane_count); > > + > > + do { > > + train_retries++; > > + if (!mtk_dp->train_info.cable_plugged_in || > > + mtk_dp->train_info.irq_sta.hpd_disconnect) { > > In mtk_dp_hpd_isr_handler(), train_info.irq_sta.hpd_disconnect would > finally be set to false, so you need not to check it here. So remove > it > here. > Hello CK, ok, I will drop this. > > + return -ENODEV; > > + } > > + > > + if (mtk_dp->train_state < MTK_DP_TRAIN_STATE_TRAINING) > > + return -EAGAIN; > > + > > + if (!pass_tps1) { > > + ret = mtk_dp_train_tps_1(mtk_dp, > > target_lane_count, > > + &iteration_count, > > lane_adjust, > > + &status_control, > > + &prev_lane_adjust); > > + if (!ret) { > > + pass_tps1 = true; > > + train_retries = 0; > > + } else if (ret == -EINVAL) { > > + break; > > + } > > + } else { > > + ret = mtk_dp_train_tps_2_3(mtk_dp, > > target_link_rate, > > + target_lane_count, > > + &iteration_count, > > + lane_adjust, > > &status_control, > > + &prev_lane_adjust); > > + if (!ret) { > > + pass_tps2_3 = true; > > + break; > > + } else if (ret == -EINVAL) { > > + break; > > + } > > + } > > + > > + drm_dp_dpcd_read(&mtk_dp->aux, > > DP_ADJUST_REQUEST_LANE0_1, > > + lane_adjust, sizeof(lane_adjust)); > > + mtk_dp_train_update_swing_pre(mtk_dp, > > target_lane_count, > > + lane_adjust); > > + } while (train_retries < MTK_DP_TRAIN_RETRY_LIMIT && > > + iteration_count < MTK_DP_TRAIN_MAX_ITERATIONS); > > + > > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET, > > + DP_TRAINING_PATTERN_DISABLE); > > + ret = mtk_dp_train_set_pattern(mtk_dp, 0); > > + if (ret) > > + return -EINVAL; > > + > > + if (!pass_tps2_3) > > + return -ETIMEDOUT; > > + > > + mtk_dp->train_info.link_rate = target_link_rate; > > + mtk_dp->train_info.lane_count = target_lane_count; > > + > > + mtk_dp_training_set_scramble(mtk_dp, true); > > + > > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET, > > + target_lane_count | > > + DP_LANE_COUNT_ENHANCED_FRAME_EN); > > + mtk_dp_set_enhanced_frame_mode(mtk_dp, true); > > + > > + return ret; > > +} > > + > > [snip] > > > + > > +/* > > + * We need to handle HPD signal in eDP even though eDP is a always > > connected > > + * device. Besides connected status, there is another feature for > > HPD signal - > > + * HPD pulse: it presents an IRQ from sink devices to source > > devices > > (Refer to > > + * 5.1.4 of DP1.4 spec). > > + */ > > +static irqreturn_t mtk_dp_hpd_isr_handler(struct mtk_dp *mtk_dp) > > +{ > > + bool connected; > > + u32 irq_status = mtk_dp_swirq_get_clear(mtk_dp) | > > + mtk_dp_hwirq_get_clear(mtk_dp); > > + struct mtk_dp_train_info *train_info = &mtk_dp->train_info; > > + > > + if (irq_status & MTK_DP_HPD_INTERRUPT) > > + train_info->irq_sta.hpd_inerrupt = true; > > + if (irq_status & MTK_DP_HPD_CONNECT) > > + train_info->irq_sta.hpd_connect = true; > > + if (irq_status & MTK_DP_HPD_DISCONNECT) > > + train_info->irq_sta.hpd_disconnect = true; > > + > > train_info->irq_sta.hpd_connect is used only in this function, so let > hpd_connect to be local variable. > ok > > + if (!irq_status) > > + return IRQ_HANDLED; > > + > > + connected = mtk_dp_plug_state(mtk_dp); > > + if (connected || !train_info->cable_plugged_in) > > + train_info->irq_sta.hpd_disconnect = false; > > + else if (!connected || train_info->cable_plugged_in) > > + train_info->irq_sta.hpd_connect = false; > > + > > + if (!(train_info->irq_sta.hpd_connect || > > + train_info->irq_sta.hpd_disconnect)) > > + return IRQ_WAKE_THREAD; > > + > > + if (train_info->irq_sta.hpd_connect) { > > + train_info->irq_sta.hpd_connect = false; > > + train_info->cable_plugged_in = true; > > + } else { > > + train_info->irq_sta.hpd_disconnect = false; > > + train_info->cable_plugged_in = false; > > + mtk_dp->train_state = MTK_DP_TRAIN_STATE_TRAINING; > > + } > > + train_info->cable_state_change = true; > > + > > + return IRQ_WAKE_THREAD; > > +} > > + > > [snip] > > > + > > +static ssize_t mtk_dp_aux_transfer(struct drm_dp_aux *mtk_aux, > > + struct drm_dp_aux_msg *msg) > > +{ > > + struct mtk_dp *mtk_dp; > > + bool is_read; > > + u8 request; > > + size_t accessed_bytes = 0; > > + int ret = 0; > > + > > + mtk_dp = container_of(mtk_aux, struct mtk_dp, aux); > > + > > + if (!mtk_dp->train_info.cable_plugged_in || > > + mtk_dp->train_info.irq_sta.hpd_disconnect) { > > In mtk_dp_hpd_isr_handler(), train_info.irq_sta.hpd_disconnect would > finally be set to false, so you need not to check it here. So remove > it > here. > ok, I will drop this BRs, Bo-Chen > Regards, > CK > > > + ret = -EAGAIN; > > + goto err; > > + } > > + > > + switch (msg->request) { > > + case DP_AUX_I2C_MOT: > > + case DP_AUX_I2C_WRITE: > > + case DP_AUX_NATIVE_WRITE: > > + case DP_AUX_I2C_WRITE_STATUS_UPDATE: > > + case DP_AUX_I2C_WRITE_STATUS_UPDATE | DP_AUX_I2C_MOT: > > + request = msg->request & > > ~DP_AUX_I2C_WRITE_STATUS_UPDATE; > > + is_read = false; > > + break; > > + case DP_AUX_I2C_READ: > > + case DP_AUX_NATIVE_READ: > > + case DP_AUX_I2C_READ | DP_AUX_I2C_MOT: > > + request = msg->request; > > + is_read = true; > > + break; > > + default: > > + drm_err(mtk_aux->drm_dev, "invalid aux cmd = %d\n", > > + msg->request); > > + ret = -EINVAL; > > + goto err; > > + } > > + > > + if (msg->size == 0) { > > + ret = mtk_dp_aux_do_transfer(mtk_dp, is_read, request, > > + msg->address + > > accessed_bytes, > > + msg->buffer + > > accessed_bytes, 0); > > + } else { > > + while (accessed_bytes < msg->size) { > > + size_t to_access = > > + min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES, > > + msg->size - accessed_bytes); > > + > > + ret = mtk_dp_aux_do_transfer(mtk_dp, is_read, > > request, > > + msg->address + > > accessed_bytes, > > + msg->buffer + > > accessed_bytes, > > + to_access); > > + > > + if (ret) { > > + drm_info(mtk_dp->drm_dev, > > + "Failed to do AUX transfer: > > %d\n", ret); > > + break; > > + } > > + accessed_bytes += to_access; > > + } > > + } > > +err: > > + if (ret) { > > + msg->reply = DP_AUX_NATIVE_REPLY_NACK | > > DP_AUX_I2C_REPLY_NACK; > > + return ret; > > + } > > + > > + msg->reply = DP_AUX_NATIVE_REPLY_ACK | DP_AUX_I2C_REPLY_ACK; > > + return msg->size; > > +} > > + > >
On Wed, 2022-06-15 at 11:06 +0800, CK Hu wrote: > Hi, Bo-Chen: > > On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > > From: Markus Schneider-Pargmann <msp@baylibre.com> > > > > This patch adds a embedded displayport driver for the MediaTek > > mt8195 > > SoC. > > > > It supports the MT8195, the embedded DisplayPort units. It offers > > DisplayPort 1.4 with up to 4 lanes. > > > > The driver creates a child device for the phy. The child device > > will > > never exist without the parent being active. As they are sharing a > > register range, the parent passes a regmap pointer to the child so > > that > > both can work with the same register range. The phy driver sets > > device > > data that is read by the parent to get the phy device that can be > > used > > to control the phy properties. > > > > This driver is based on an initial version by > > Jitao shi <jitao.shi@mediatek.com> > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > > --- > > [snip] > > > + > > +static int mtk_dp_parse_capabilities(struct mtk_dp *mtk_dp) > > +{ > > + u8 val; > > + struct mtk_dp_train_info *train_info = &mtk_dp->train_info; > > + > > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, > > DP_SET_POWER_D0); > > + usleep_range(2000, 5000); > > + > > + drm_dp_read_dpcd_caps(&mtk_dp->aux, mtk_dp->rx_cap); > > + > > + mtk_dp->rx_cap[DP_TRAINING_AUX_RD_INTERVAL] &= > > DP_TRAINING_AUX_RD_MASK; > > + > > + train_info->link_rate = min_t(int, mtk_dp->max_linkrate, > > + mtk_dp->rx_cap[mtk_dp- > > > max_linkrate]); > > > > + train_info->lane_count = min_t(int, mtk_dp->max_lanes, > > + drm_dp_max_lane_count(mtk_dp- > > > rx_cap)); > > > > + > > + train_info->tps3 = drm_dp_tps3_supported(mtk_dp->rx_cap); > > + train_info->tps4 = drm_dp_tps4_supported(mtk_dp->rx_cap); > > + > > + train_info->sink_ssc = !!(mtk_dp->rx_cap[DP_MAX_DOWNSPREAD] & > > + DP_MAX_DOWNSPREAD_0_5); > > I think this is redundant because next statement would set sink_scc > to > false. > > Regards, > CK > Hello Ck, I will remove "train_info->sink_ssc = false;" BRs, Bo-Chen > > + > > + train_info->sink_ssc = false; > > + > > + drm_dp_dpcd_readb(&mtk_dp->aux, DP_MSTM_CAP, &val); > > + if (val & DP_MST_CAP) { > > + /* Clear DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 */ > > + drm_dp_dpcd_readb(&mtk_dp->aux, > > + DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0, > > &val); > > + if (val) > > + drm_dp_dpcd_writeb(&mtk_dp->aux, > > + DP_DEVICE_SERVICE_IRQ_VECTOR > > _ESI0, > > + val); > > + } > > + > > + return 0; > > +} > >
On Wed, 2022-06-15 at 13:50 +0800, CK Hu wrote: > Hi, Bo-Chen: > > On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > > From: Markus Schneider-Pargmann <msp@baylibre.com> > > > > This patch adds a embedded displayport driver for the MediaTek > > mt8195 > > SoC. > > > > It supports the MT8195, the embedded DisplayPort units. It offers > > DisplayPort 1.4 with up to 4 lanes. > > > > The driver creates a child device for the phy. The child device > > will > > never exist without the parent being active. As they are sharing a > > register range, the parent passes a regmap pointer to the child so > > that > > both can work with the same register range. The phy driver sets > > device > > data that is read by the parent to get the phy device that can be > > used > > to control the phy properties. > > > > This driver is based on an initial version by > > Jitao shi <jitao.shi@mediatek.com> > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > > --- > > [snip] > > > + > > +static int mtk_dp_train_flow(struct mtk_dp *mtk_dp, u8 > > target_link_rate, > > + u8 target_lane_count) > > +{ > > + u8 lane_adjust[2] = {}; > > + bool pass_tps1 = false; > > + bool pass_tps2_3 = false; > > + int train_retries; > > + int status_control; > > + int iteration_count; > > + int ret; > > + u8 prev_lane_adjust; > > + > > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LINK_BW_SET, > > target_link_rate); > > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET, > > + target_lane_count | > > DP_LANE_COUNT_ENHANCED_FRAME_EN); > > + > > + if (mtk_dp->train_info.sink_ssc) > > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_DOWNSPREAD_CTRL, > > + DP_SPREAD_AMP_0_5); > > + > > + train_retries = 0; > > + status_control = 0; > > + iteration_count = 1; > > + prev_lane_adjust = 0xFF; > > + > > + mtk_dp_set_lanes(mtk_dp, target_lane_count / 2); > > + ret = mtk_dp_phy_configure(mtk_dp, target_link_rate, > > target_lane_count); > > + if (ret) > > + return -EINVAL; > > + > > + dev_dbg(mtk_dp->dev, > > + "Link train target_link_rate = 0x%x, target_lane_count > > = 0x%x\n", > > + target_link_rate, target_lane_count); > > + > > + do { > > + train_retries++; > > + if (!mtk_dp->train_info.cable_plugged_in || > > + mtk_dp->train_info.irq_sta.hpd_disconnect) { > > + return -ENODEV; > > + } > > + > > + if (mtk_dp->train_state < MTK_DP_TRAIN_STATE_TRAINING) > > This checking would never be true, so remove it. > Hello CK, ok, I will do this. > > + return -EAGAIN; > > + > > + if (!pass_tps1) { > > + ret = mtk_dp_train_tps_1(mtk_dp, > > target_lane_count, > > + &iteration_count, > > lane_adjust, > > + &status_control, > > + &prev_lane_adjust); > > + if (!ret) { > > + pass_tps1 = true; > > + train_retries = 0; > > + } else if (ret == -EINVAL) { > > + break; > > + } > > + } else { > > + ret = mtk_dp_train_tps_2_3(mtk_dp, > > target_link_rate, > > + target_lane_count, > > + &iteration_count, > > + lane_adjust, > > &status_control, > > + &prev_lane_adjust); > > + if (!ret) { > > + pass_tps2_3 = true; > > + break; > > + } else if (ret == -EINVAL) { > > + break; > > + } > > + } > > + > > + drm_dp_dpcd_read(&mtk_dp->aux, > > DP_ADJUST_REQUEST_LANE0_1, > > + lane_adjust, sizeof(lane_adjust)); > > + mtk_dp_train_update_swing_pre(mtk_dp, > > target_lane_count, > > + lane_adjust); > > + } while (train_retries < MTK_DP_TRAIN_RETRY_LIMIT && > > + iteration_count < MTK_DP_TRAIN_MAX_ITERATIONS); > > mtk_dp_train_tps_1() & mtk_dp_train_tps_2_3() would only be called > once > and never be called twice, so remove this loop. > > Regards, > CK > > > + > > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_TRAINING_PATTERN_SET, > > + DP_TRAINING_PATTERN_DISABLE); > > + ret = mtk_dp_train_set_pattern(mtk_dp, 0); > > + if (ret) > > + return -EINVAL; > > + > > + if (!pass_tps2_3) > > + return -ETIMEDOUT; > > + > > + mtk_dp->train_info.link_rate = target_link_rate; > > + mtk_dp->train_info.lane_count = target_lane_count; > > + > > + mtk_dp_training_set_scramble(mtk_dp, true); > > + > > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_LANE_COUNT_SET, > > + target_lane_count | > > + DP_LANE_COUNT_ENHANCED_FRAME_EN); > > + mtk_dp_set_enhanced_frame_mode(mtk_dp, true); > > + > > + return ret; > > +} > >
On Wed, 2022-06-15 at 13:53 +0800, CK Hu wrote: > Hi, Bo-Chen: > > On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > > From: Markus Schneider-Pargmann <msp@baylibre.com> > > > > This patch adds a embedded displayport driver for the MediaTek > > mt8195 > > SoC. > > > > It supports the MT8195, the embedded DisplayPort units. It offers > > DisplayPort 1.4 with up to 4 lanes. > > > > The driver creates a child device for the phy. The child device > > will > > never exist without the parent being active. As they are sharing a > > register range, the parent passes a regmap pointer to the child so > > that > > both can work with the same register range. The phy driver sets > > device > > data that is read by the parent to get the phy device that can be > > used > > to control the phy properties. > > > > This driver is based on an initial version by > > Jitao shi <jitao.shi@mediatek.com> > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > > --- > > [snip] > > > + > > +static int mtk_dp_train_set_pattern(struct mtk_dp *mtk_dp, int > > pattern) > > +{ > > + if (pattern < 0 || pattern > 4) { > > The caller would pass pattern from 0 to 4, so this checking is > redundant. Remove it and this function would always return true, so > let > this function be void. > > Regards, > CK > Hello CK, ok, I will do this. BRs, Bo-Chen > > + drm_err(mtk_dp->drm_dev, > > + "Implementation error, no such pattern %d\n", > > pattern); > > + return -EINVAL; > > + } > > + > > + /* TPS1 */ > > + if (pattern == 1) > > + mtk_dp_set_idle_pattern(mtk_dp, false); > > + > > + mtk_dp_update_bits(mtk_dp, > > + MTK_DP_TRANS_P0_3400, > > + pattern ? > > + BIT(pattern - 1) << > > PATTERN1_EN_DP_TRANS_P0_SHIFT : > > + 0, > > + PATTERN1_EN_DP_TRANS_P0_MASK | > > + PATTERN2_EN_DP_TRANS_P0_MASK | > > + PATTERN3_EN_DP_TRANS_P0_MASK | > > + PATTERN4_EN_DP_TRANS_P0_MASK); > > + return 0; > > +} > >
On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@mediatek.com> > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- [snip] > + > +static void mtk_dp_calculate_pixrate(struct mtk_dp *mtk_dp) > +{ > + u8 target_frame_rate = 60; > + u32 target_pixel_clk; > + struct drm_display_mode mode; > + struct mtk_dp_timings *timings = &mtk_dp->info.timings; > + > + drm_display_mode_from_videomode(&timings->vm, &mode); > + > + if (mtk_dp->info.timings.frame_rate > 0) { > + target_frame_rate = mtk_dp->info.timings.frame_rate; > + target_pixel_clk = mode.htotal * mode.vtotal * > + target_frame_rate; > + } else if (mtk_dp->info.timings.pix_rate_khz > 0) { > + target_pixel_clk = mtk_dp->info.timings.pix_rate_khz * > 1000; > + } else { > + target_pixel_clk = mode.htotal * mode.vtotal * > + target_frame_rate; > + } > + > + mtk_dp->info.timings.pix_rate_khz = target_pixel_clk / 1000; It seems that pix_rate_khz is used only here and does not used in another place, so pix_rate_khz is useless, remove it. Regards, CK > +} > +
On Mon, 2022-06-20 at 11:12 +0800, CK Hu wrote: > On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > > From: Markus Schneider-Pargmann <msp@baylibre.com> > > > > This patch adds a embedded displayport driver for the MediaTek > > mt8195 > > SoC. > > > > It supports the MT8195, the embedded DisplayPort units. It offers > > DisplayPort 1.4 with up to 4 lanes. > > > > The driver creates a child device for the phy. The child device > > will > > never exist without the parent being active. As they are sharing a > > register range, the parent passes a regmap pointer to the child so > > that > > both can work with the same register range. The phy driver sets > > device > > data that is read by the parent to get the phy device that can be > > used > > to control the phy properties. > > > > This driver is based on an initial version by > > Jitao shi <jitao.shi@mediatek.com> > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > > --- > > [snip] > > > + > > +static void mtk_dp_calculate_pixrate(struct mtk_dp *mtk_dp) > > +{ > > + u8 target_frame_rate = 60; > > + u32 target_pixel_clk; > > + struct drm_display_mode mode; > > + struct mtk_dp_timings *timings = &mtk_dp->info.timings; > > + > > + drm_display_mode_from_videomode(&timings->vm, &mode); > > + > > + if (mtk_dp->info.timings.frame_rate > 0) { > > + target_frame_rate = mtk_dp->info.timings.frame_rate; > > + target_pixel_clk = mode.htotal * mode.vtotal * > > + target_frame_rate; > > + } else if (mtk_dp->info.timings.pix_rate_khz > 0) { > > + target_pixel_clk = mtk_dp->info.timings.pix_rate_khz * > > 1000; > > + } else { > > + target_pixel_clk = mode.htotal * mode.vtotal * > > + target_frame_rate; > > + } > > + > > + mtk_dp->info.timings.pix_rate_khz = target_pixel_clk / 1000; > > It seems that pix_rate_khz is used only here and does not used in > another place, so pix_rate_khz is useless, remove it. It seems that frame_rate is also redundant, so remove it. Regards, CK > > Regards, > CK > > > +} > > +
Hi, Rex: On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@mediatek.com> > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- [snip] > + > +static void mtk_dp_set_color_depth(struct mtk_dp *mtk_dp, u32 > color_depth) In the whole driver, the color_depth would only be DP_MSA_MISC_8_BPC, so remove the parameter color_depth and fix the color depth to DP_MSA_MISC_8_BPC in this function. Regards, CK > +{ > + u32 val; > + > + mtk_dp->info.depth = color_depth; > + > + /* Update MISC0 */ > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_3034, > + color_depth, DP_TEST_BIT_DEPTH_MASK); > + > + switch (color_depth) { > + case DP_MSA_MISC_6_BPC: > + val = VIDEO_COLOR_DEPTH_DP_ENC0_P0_6BIT; > + break; > + case DP_MSA_MISC_8_BPC: > + val = VIDEO_COLOR_DEPTH_DP_ENC0_P0_8BIT; > + break; > + case DP_MSA_MISC_10_BPC: > + val = VIDEO_COLOR_DEPTH_DP_ENC0_P0_10BIT; > + break; > + case DP_MSA_MISC_12_BPC: > + val = VIDEO_COLOR_DEPTH_DP_ENC0_P0_12BIT; > + break; > + case DP_MSA_MISC_16_BPC: > + val = VIDEO_COLOR_DEPTH_DP_ENC0_P0_16BIT; > + break; > + default: > + drm_warn(mtk_dp->drm_dev, "Unsupported color depth > %d\n", > + color_depth); > + return; > + } > + > + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_303C, val, > + VIDEO_COLOR_DEPTH_DP_ENC0_P0_MASK); > +} > +
Hi, Rex: On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@mediatek.com> > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- [snip] > + > +static void mtk_dp_poweroff(struct mtk_dp *mtk_dp) > +{ > + mutex_lock(&mtk_dp->dp_lock); > + > + mtk_dp_hwirq_enable(mtk_dp, false); > + mtk_dp_power_disable(mtk_dp); > + phy_exit(mtk_dp->phy); > + > + mutex_unlock(&mtk_dp->dp_lock); > +} > + > +static int mtk_dp_poweron(struct mtk_dp *mtk_dp) > +{ > + int ret = 0; > + > + mutex_lock(&mtk_dp->dp_lock); The dp_poweron/off is only called by bridge_attach/detach, and I think drm core would not call attach/detach concurrently, so this mutex is redundant. Remove it. Regards, CK > + > + ret = phy_init(mtk_dp->phy); > + if (ret) { > + dev_err(mtk_dp->dev, "Failed to initialize phy: %d\n", > ret); > + goto err_phy_init; > + } > + ret = mtk_dp_phy_configure(mtk_dp, MTK_DP_LINKRATE_RBR, 1); > + if (ret) { > + dev_err(mtk_dp->dev, "Failed to configure phy: %d\n", > ret); > + goto err_phy_config; > + } > + > + mtk_dp_init_port(mtk_dp); > + mtk_dp_power_enable(mtk_dp); > + > +err_phy_config: > + phy_exit(mtk_dp->phy); > +err_phy_init: > + mutex_unlock(&mtk_dp->dp_lock); > + return ret; > +}
Hi, Rex: On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@mediatek.com> > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- [snip] > + > +static int mtk_dp_bridge_atomic_check(struct drm_bridge *bridge, > + struct drm_bridge_state > *bridge_state, > + struct drm_crtc_state > *crtc_state, > + struct drm_connector_state > *conn_state) > +{ > + struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge); > + struct drm_crtc *crtc = conn_state->crtc; > + unsigned int input_bus_format; > + > + input_bus_format = bridge_state->input_bus_cfg.format; > + > + dev_dbg(mtk_dp->dev, "input format 0x%04x, output format > 0x%04x\n", > + bridge_state->input_bus_cfg.format, > + bridge_state->output_bus_cfg.format); > + > + mtk_dp->input_fmt = input_bus_format; > + if (mtk_dp->input_fmt == MEDIA_BUS_FMT_YUYV8_1X16) input_fmt is used only in this function, so let it be local variable. Regards, CK > + mtk_dp->info.format = DP_PIXELFORMAT_YUV422; > + else > + mtk_dp->info.format = DP_PIXELFORMAT_RGB; > + > + if (!crtc) { > + drm_err(mtk_dp->drm_dev, > + "Can't enable bridge as connector state doesn't > have a crtc\n"); > + return -EINVAL; > + } > + > + mtk_dp_parse_drm_mode_timings(mtk_dp, &crtc_state- > >adjusted_mode); > + if (mtk_dp_parse_capabilities(mtk_dp)) { > + drm_err(mtk_dp->drm_dev, > + "Can't enable bridge as nothing is plugged > in\n"); > + return -EINVAL; > + } > + > + return 0; > +}
Hi, Bo-Chen: On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@mediatek.com> > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- [snip] > + > +static int mtk_dp_probe(struct platform_device *pdev) > +{ > + struct mtk_dp *mtk_dp; > + struct device *dev = &pdev->dev; > + int ret; > + int irq_num = 0; > + > + mtk_dp = devm_kzalloc(dev, sizeof(*mtk_dp), GFP_KERNEL); > + if (!mtk_dp) > + return -ENOMEM; > + > + mtk_dp->dev = dev; > + > + irq_num = platform_get_irq(pdev, 0); > + if (irq_num < 0) > + return dev_err_probe(dev, irq_num, > + "failed to request dp irq > resource\n"); > + > + mtk_dp->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, > 1, 0); > + if (IS_ERR(mtk_dp->next_bridge)) > + return dev_err_probe(dev, PTR_ERR(mtk_dp->next_bridge), > + "Failed to get bridge\n"); > + > + ret = mtk_dp_dt_parse(mtk_dp, pdev); > + if (ret) > + return dev_err_probe(dev, ret, "Failed to parse dt\n"); > + > + drm_dp_aux_init(&mtk_dp->aux); > + mtk_dp->aux.name = "aux_mtk_dp"; > + mtk_dp->aux.transfer = mtk_dp_aux_transfer; In the comment of drm_dp_aux_init(), drm_dp_aux_init() is used before drm_dp_aux_register(). So I think we still need to call drm_dp_aux_register(). Regards, CK > + > + ret = devm_request_threaded_irq(dev, irq_num, mtk_dp_hpd_event, > + mtk_dp_hpd_event_thread, > + IRQ_TYPE_LEVEL_HIGH, > dev_name(dev), > + mtk_dp); > + if (ret) > + return dev_err_probe(dev, -EPROBE_DEFER, > + "failed to request mediatek dptx > irq\n"); > + > + mutex_init(&mtk_dp->dp_lock); > + > + platform_set_drvdata(pdev, mtk_dp); > + > + mtk_dp->phy_dev = platform_device_register_data(dev, "mediatek- > dp-phy", > + PLATFORM_DEVID_ > AUTO, > + &mtk_dp->regs, > + sizeof(struct > regmap *)); > + if (IS_ERR(mtk_dp->phy_dev)) > + return dev_err_probe(dev, PTR_ERR(mtk_dp->phy_dev), > + "Failed to create device mediatek- > dp-phy\n"); > + > + mtk_dp_get_calibration_data(mtk_dp); > + > + mtk_dp->phy = devm_phy_get(&mtk_dp->phy_dev->dev, "dp"); > + > + if (IS_ERR(mtk_dp->phy)) { > + platform_device_unregister(mtk_dp->phy_dev); > + return dev_err_probe(dev, PTR_ERR(mtk_dp->phy), > + "Failed to get phy\n"); > + } > + > + mtk_dp->bridge.funcs = &mtk_dp_bridge_funcs; > + mtk_dp->bridge.of_node = dev->of_node; > + > + mtk_dp->bridge.ops = > + DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | > DRM_BRIDGE_OP_HPD; > + mtk_dp->bridge.type = DRM_MODE_CONNECTOR_eDP; > + > + drm_bridge_add(&mtk_dp->bridge); > + > + pm_runtime_enable(dev); > + pm_runtime_get_sync(dev); > + > + return 0; > +}
Hi, Bo-Chen: On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@mediatek.com> > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- [snip] > + > +#define MTK_DP_ENC0_P0_3130 (ENC0_OFFSET + 0x130) This is useless in this patch, so remove it. If this is used in later patch, add this back in that patch. > +#define MTK_DP_ENC0_P0_3138 (ENC0_OFFSET + 0x138) Ditto. Regards, CK > +#define MTK_DP_ENC0_P0_3154 (ENC0_OFFSET + 0x154) > +#define PGEN_HTOTAL_DP_ENC0_P0_MASK GENMASK(13, 0) > +#define MTK_DP_ENC0_P0_3158 (ENC0_OFFSET + 0x158) >
Hi, Bo-Chen: On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@mediatek.com> > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- [snip] > + > +static int mtk_dp_parse_capabilities(struct mtk_dp *mtk_dp) > +{ > + u8 val; > + struct mtk_dp_train_info *train_info = &mtk_dp->train_info; > + > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, > DP_SET_POWER_D0); > + usleep_range(2000, 5000); > + > + drm_dp_read_dpcd_caps(&mtk_dp->aux, mtk_dp->rx_cap); > + > + mtk_dp->rx_cap[DP_TRAINING_AUX_RD_INTERVAL] &= > DP_TRAINING_AUX_RD_MASK; > + > + train_info->link_rate = min_t(int, mtk_dp->max_linkrate, > + mtk_dp->rx_cap[mtk_dp- > >max_linkrate]); drm_dp_max_link_rate(mtk_dp->rx_cap) Regards, CK > + train_info->lane_count = min_t(int, mtk_dp->max_lanes, > + drm_dp_max_lane_count(mtk_dp- > >rx_cap)); > + > + train_info->tps3 = drm_dp_tps3_supported(mtk_dp->rx_cap); > + train_info->tps4 = drm_dp_tps4_supported(mtk_dp->rx_cap); > + > + train_info->sink_ssc = !!(mtk_dp->rx_cap[DP_MAX_DOWNSPREAD] & > + DP_MAX_DOWNSPREAD_0_5); > + > + train_info->sink_ssc = false; > + > + drm_dp_dpcd_readb(&mtk_dp->aux, DP_MSTM_CAP, &val); > + if (val & DP_MST_CAP) { > + /* Clear DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 */ > + drm_dp_dpcd_readb(&mtk_dp->aux, > + DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0, > &val); > + if (val) > + drm_dp_dpcd_writeb(&mtk_dp->aux, > + DP_DEVICE_SERVICE_IRQ_VECTOR > _ESI0, > + val); > + } > + > + return 0; > +}
Hi, Bo-Chen: On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@mediatek.com> > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- [snip] > + > +/* multiple of 0.27Gbps */ > +enum mtk_dp_linkrate { > + MTK_DP_LINKRATE_RBR = 0x6, > + MTK_DP_LINKRATE_HBR = 0xA, > + MTK_DP_LINKRATE_HBR2 = 0x14, > + MTK_DP_LINKRATE_HBR25 = 0x19, > + MTK_DP_LINKRATE_HBR3 = 0x1E, > +}; Use the definition in drm_dp.h: /* Link Configuration */ #define DP_LINK_BW_SET 0x100 # define DP_LINK_RATE_TABLE 0x00 /* eDP 1.4 */ # define DP_LINK_BW_1_62 0x06 # define DP_LINK_BW_2_7 0x0a # define DP_LINK_BW_5_4 0x14 /* 1.2 */ # define DP_LINK_BW_8_1 0x1e /* 1.4 */ # define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */ # define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */ # define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */ Regards, CK > >
Hi, Bo-Chen: On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > From: Markus Schneider-Pargmann <msp@baylibre.com> > > This patch adds a embedded displayport driver for the MediaTek mt8195 > SoC. > > It supports the MT8195, the embedded DisplayPort units. It offers > DisplayPort 1.4 with up to 4 lanes. > > The driver creates a child device for the phy. The child device will > never exist without the parent being active. As they are sharing a > register range, the parent passes a regmap pointer to the child so > that > both can work with the same register range. The phy driver sets > device > data that is read by the parent to get the phy device that can be > used > to control the phy properties. > > This driver is based on an initial version by > Jitao shi <jitao.shi@mediatek.com> > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > --- [snip] > + > +static int mtk_dp_parse_capabilities(struct mtk_dp *mtk_dp) > +{ > + u8 val; > + struct mtk_dp_train_info *train_info = &mtk_dp->train_info; > + > + drm_dp_dpcd_writeb(&mtk_dp->aux, DP_SET_POWER, > DP_SET_POWER_D0); > + usleep_range(2000, 5000); > + > + drm_dp_read_dpcd_caps(&mtk_dp->aux, mtk_dp->rx_cap); > + > + mtk_dp->rx_cap[DP_TRAINING_AUX_RD_INTERVAL] &= > DP_TRAINING_AUX_RD_MASK; You never use mtk_dp->rx_cap[DP_TRAINING_AUX_RD_INTERVAL], why do you modify it? > + > + train_info->link_rate = min_t(int, mtk_dp->max_linkrate, > + mtk_dp->rx_cap[mtk_dp- > >max_linkrate]); > + train_info->lane_count = min_t(int, mtk_dp->max_lanes, > + drm_dp_max_lane_count(mtk_dp- > >rx_cap)); > + > + train_info->tps3 = drm_dp_tps3_supported(mtk_dp->rx_cap); > + train_info->tps4 = drm_dp_tps4_supported(mtk_dp->rx_cap); > + > + train_info->sink_ssc = !!(mtk_dp->rx_cap[DP_MAX_DOWNSPREAD] & > + DP_MAX_DOWNSPREAD_0_5); > + train_info->sink_ssc = drm_dp_max_downspread(mtk_dp->rx_cap); Regards, CK > + train_info->sink_ssc = false; > + > + drm_dp_dpcd_readb(&mtk_dp->aux, DP_MSTM_CAP, &val); > + if (val & DP_MST_CAP) { > + /* Clear DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0 */ > + drm_dp_dpcd_readb(&mtk_dp->aux, > + DP_DEVICE_SERVICE_IRQ_VECTOR_ESI0, > &val); > + if (val) > + drm_dp_dpcd_writeb(&mtk_dp->aux, > + DP_DEVICE_SERVICE_IRQ_VECTOR > _ESI0, > + val); > + } > + > + return 0; > +}
On Mon, 2022-06-20 at 11:12 +0800, CK Hu wrote: > On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > > From: Markus Schneider-Pargmann <msp@baylibre.com> > > > > This patch adds a embedded displayport driver for the MediaTek > > mt8195 > > SoC. > > > > It supports the MT8195, the embedded DisplayPort units. It offers > > DisplayPort 1.4 with up to 4 lanes. > > > > The driver creates a child device for the phy. The child device > > will > > never exist without the parent being active. As they are sharing a > > register range, the parent passes a regmap pointer to the child so > > that > > both can work with the same register range. The phy driver sets > > device > > data that is read by the parent to get the phy device that can be > > used > > to control the phy properties. > > > > This driver is based on an initial version by > > Jitao shi <jitao.shi@mediatek.com> > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > > --- > > [snip] > > > + > > +static void mtk_dp_calculate_pixrate(struct mtk_dp *mtk_dp) > > +{ > > + u8 target_frame_rate = 60; > > + u32 target_pixel_clk; > > + struct drm_display_mode mode; > > + struct mtk_dp_timings *timings = &mtk_dp->info.timings; > > + > > + drm_display_mode_from_videomode(&timings->vm, &mode); > > + > > + if (mtk_dp->info.timings.frame_rate > 0) { > > + target_frame_rate = mtk_dp->info.timings.frame_rate; > > + target_pixel_clk = mode.htotal * mode.vtotal * > > + target_frame_rate; > > + } else if (mtk_dp->info.timings.pix_rate_khz > 0) { > > + target_pixel_clk = mtk_dp->info.timings.pix_rate_khz * > > 1000; > > + } else { > > + target_pixel_clk = mode.htotal * mode.vtotal * > > + target_frame_rate; > > + } > > + > > + mtk_dp->info.timings.pix_rate_khz = target_pixel_clk / 1000; > > It seems that pix_rate_khz is used only here and does not used in > another place, so pix_rate_khz is useless, remove it. > > Regards, > CK > this variable will be used in audio patch. I will move it to audio patch. BRs, Bo-Chen > > +} > > + > >
On Mon, 2022-06-20 at 11:19 +0800, CK Hu wrote: > On Mon, 2022-06-20 at 11:12 +0800, CK Hu wrote: > > On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > > > From: Markus Schneider-Pargmann <msp@baylibre.com> > > > > > > This patch adds a embedded displayport driver for the MediaTek > > > mt8195 > > > SoC. > > > > > > It supports the MT8195, the embedded DisplayPort units. It offers > > > DisplayPort 1.4 with up to 4 lanes. > > > > > > The driver creates a child device for the phy. The child device > > > will > > > never exist without the parent being active. As they are sharing > > > a > > > register range, the parent passes a regmap pointer to the child > > > so > > > that > > > both can work with the same register range. The phy driver sets > > > device > > > data that is read by the parent to get the phy device that can be > > > used > > > to control the phy properties. > > > > > > This driver is based on an initial version by > > > Jitao shi <jitao.shi@mediatek.com> > > > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > > > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > > > --- > > > > [snip] > > > > > + > > > +static void mtk_dp_calculate_pixrate(struct mtk_dp *mtk_dp) > > > +{ > > > + u8 target_frame_rate = 60; > > > + u32 target_pixel_clk; > > > + struct drm_display_mode mode; > > > + struct mtk_dp_timings *timings = &mtk_dp->info.timings; > > > + > > > + drm_display_mode_from_videomode(&timings->vm, &mode); > > > + > > > + if (mtk_dp->info.timings.frame_rate > 0) { > > > + target_frame_rate = mtk_dp->info.timings.frame_rate; > > > + target_pixel_clk = mode.htotal * mode.vtotal * > > > + target_frame_rate; > > > + } else if (mtk_dp->info.timings.pix_rate_khz > 0) { > > > + target_pixel_clk = mtk_dp->info.timings.pix_rate_khz * > > > 1000; > > > + } else { > > > + target_pixel_clk = mode.htotal * mode.vtotal * > > > + target_frame_rate; > > > + } > > > + > > > + mtk_dp->info.timings.pix_rate_khz = target_pixel_clk / 1000; > > > > It seems that pix_rate_khz is used only here and does not used in > > another place, so pix_rate_khz is useless, remove it. > > It seems that frame_rate is also redundant, so remove it. > > Regards, > CK > I think we do use this variable in mtk_dp_parse_drm_mode_timings() We use this variable to get target framerate. BRs, Bo-Chen > > > > Regards, > > CK > > > > > +} > > > + > >
On Mon, 2022-06-20 at 11:54 +0800, CK Hu wrote: > Hi, Rex: > > On Fri, 2022-06-10 at 18:55 +0800, Bo-Chen Chen wrote: > > From: Markus Schneider-Pargmann <msp@baylibre.com> > > > > This patch adds a embedded displayport driver for the MediaTek > > mt8195 > > SoC. > > > > It supports the MT8195, the embedded DisplayPort units. It offers > > DisplayPort 1.4 with up to 4 lanes. > > > > The driver creates a child device for the phy. The child device > > will > > never exist without the parent being active. As they are sharing a > > register range, the parent passes a regmap pointer to the child so > > that > > both can work with the same register range. The phy driver sets > > device > > data that is read by the parent to get the phy device that can be > > used > > to control the phy properties. > > > > This driver is based on an initial version by > > Jitao shi <jitao.shi@mediatek.com> > > > > Signed-off-by: Markus Schneider-Pargmann <msp@baylibre.com> > > Signed-off-by: Guillaume Ranquet <granquet@baylibre.com> > > [Bo-Chen: Cleanup the drivers and modify comments from reviewers] > > Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> > > --- > > [snip] > > > + > > +static int mtk_dp_bridge_atomic_check(struct drm_bridge *bridge, > > + struct drm_bridge_state > > *bridge_state, > > + struct drm_crtc_state > > *crtc_state, > > + struct drm_connector_state > > *conn_state) > > +{ > > + struct mtk_dp *mtk_dp = mtk_dp_from_bridge(bridge); > > + struct drm_crtc *crtc = conn_state->crtc; > > + unsigned int input_bus_format; > > + > > + input_bus_format = bridge_state->input_bus_cfg.format; > > + > > + dev_dbg(mtk_dp->dev, "input format 0x%04x, output format > > 0x%04x\n", > > + bridge_state->input_bus_cfg.format, > > + bridge_state->output_bus_cfg.format); > > + > > + mtk_dp->input_fmt = input_bus_format; > > + if (mtk_dp->input_fmt == MEDIA_BUS_FMT_YUYV8_1X16) > > input_fmt is used only in this function, so let it be local variable. > > Regards, > CK > ok, I will do this. BRs, Bo-Chen > > + mtk_dp->info.format = DP_PIXELFORMAT_YUV422; > > + else > > + mtk_dp->info.format = DP_PIXELFORMAT_RGB; > > + > > + if (!crtc) { > > + drm_err(mtk_dp->drm_dev, > > + "Can't enable bridge as connector state doesn't > > have a crtc\n"); > > + return -EINVAL; > > + } > > + > > + mtk_dp_parse_drm_mode_timings(mtk_dp, &crtc_state- > > > adjusted_mode); > > > > + if (mtk_dp_parse_capabilities(mtk_dp)) { > > + drm_err(mtk_dp->drm_dev, > > + "Can't enable bridge as nothing is plugged > > in\n"); > > + return -EINVAL; > > + } > > + > > + return 0; > > +} > >