[RESEND,v8,00/19] Cleanup MediaTek clk reset drivers and support SoCs

In this series, we cleanup MediaTek clock reset drivers in clk/mediatek
folder. MediaTek clock reset driver is used to provide reset control
of modules controlled in clk, like infra_ao.

Changes for v8 resend:
1. Remove tested-by tag from Nícolas for MT8195/MT8186 patches.
2. Add reviewed-by tag from AngeloGioacchino.

Changes for v8:
1. Use 'enum mtk_reset_version' to replace u8 in patch 5 and 6.
2. Use lowercase '0xc' in patch 7.
3. Drop "simple-mfd" in patch 16 because it's for original reset controller.
4. v8 is based on linux-next next-20220520 and Chen-Yu's series[1].

Changes for v7:
1. v7 is based on linux-next next-20220519 and Chen-Yu's series[1].
2. Add support for MT8186.

[1]: https://patchwork.kernel.org/project/linux-mediatek/list/?series=643003

Changes for v6:
1. Add a new patch to support inuput argument index mode.
2. Revise definition in reset.h to index.

Rex-BC Chen (19):
  clk: mediatek: reset: Add reset.h
  clk: mediatek: reset: Fix written reset bit offset
  clk: mediatek: reset: Refine and reorder functions in reset.c
  clk: mediatek: reset: Extract common drivers to update function
  clk: mediatek: reset: Merge and revise reset register function
  clk: mediatek: reset: Revise structure to control reset register
  clk: mediatek: reset: Support nonsequence base offsets of reset
    registers
  clk: mediatek: reset: Support inuput argument index mode
  clk: mediatek: reset: Change return type for clock reset register
    function
  clk: mediatek: reset: Add new register reset function with device
  clk: mediatek: reset: Add reset support for simple probe
  dt-bindings: arm: mediatek: Add #reset-cells property for
    MT8192/MT8195
  dt-bindings: reset: mediatek: Add infra_ao reset index for
    MT8192/MT8195
  clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195
  arm64: dts: mediatek: Add infra #reset-cells property for MT8192
  arm64: dts: mediatek: Add infra #reset-cells property for MT8195
  dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186
  dt-bindings: arm: mediatek: Add #reset-cells property for MT8186
  clk: mediatek: reset: Add infra_ao reset support for MT8186

 .../mediatek/mediatek,mt8186-sys-clock.yaml   |   3 +
 .../mediatek/mediatek,mt8192-sys-clock.yaml   |   3 +
 .../mediatek/mediatek,mt8195-sys-clock.yaml   |   3 +
 arch/arm64/boot/dts/mediatek/mt8192.dtsi      |   1 +
 arch/arm64/boot/dts/mediatek/mt8195.dtsi      |  15 +-
 drivers/clk/mediatek/clk-mt2701-eth.c         |  10 +-
 drivers/clk/mediatek/clk-mt2701-g3d.c         |  10 +-
 drivers/clk/mediatek/clk-mt2701-hif.c         |  10 +-
 drivers/clk/mediatek/clk-mt2701.c             |  22 +-
 drivers/clk/mediatek/clk-mt2712.c             |  22 +-
 drivers/clk/mediatek/clk-mt7622-eth.c         |  10 +-
 drivers/clk/mediatek/clk-mt7622-hif.c         |  12 +-
 drivers/clk/mediatek/clk-mt7622.c             |  22 +-
 drivers/clk/mediatek/clk-mt7629-eth.c         |  10 +-
 drivers/clk/mediatek/clk-mt7629-hif.c         |  12 +-
 drivers/clk/mediatek/clk-mt8135.c             |  22 +-
 drivers/clk/mediatek/clk-mt8173.c             |  22 +-
 drivers/clk/mediatek/clk-mt8183.c             |  18 +-
 drivers/clk/mediatek/clk-mt8186-infra_ao.c    |  23 ++
 drivers/clk/mediatek/clk-mt8192.c             |  29 +++
 drivers/clk/mediatek/clk-mt8195-infra_ao.c    |  24 +++
 drivers/clk/mediatek/clk-mtk.c                |   7 +
 drivers/clk/mediatek/clk-mtk.h                |   9 +-
 drivers/clk/mediatek/reset.c                  | 198 +++++++++++++-----
 drivers/clk/mediatek/reset.h                  |  82 ++++++++
 include/dt-bindings/reset/mt8186-resets.h     |   5 +
 include/dt-bindings/reset/mt8192-resets.h     |   8 +
 include/dt-bindings/reset/mt8195-resets.h     |   6 +
 28 files changed, 523 insertions(+), 95 deletions(-)
 create mode 100644 drivers/clk/mediatek/reset.h

Il 23/05/22 11:33, Rex-BC Chen ha scritto:
> In this series, we cleanup MediaTek clock reset drivers in clk/mediatek
> folder. MediaTek clock reset driver is used to provide reset control
> of modules controlled in clk, like infra_ao.

Thanks for this very fast resend for the T-b tag fixes (and don't worry,
it happens).

Btw, in my opinion, this series is good to go.

Cheers,
Angelo

> 
> Changes for v8 resend:
> 1. Remove tested-by tag from Nícolas for MT8195/MT8186 patches.
> 2. Add reviewed-by tag from AngeloGioacchino.
> 
> Changes for v8:
> 1. Use 'enum mtk_reset_version' to replace u8 in patch 5 and 6.
> 2. Use lowercase '0xc' in patch 7.
> 3. Drop "simple-mfd" in patch 16 because it's for original reset controller.
> 4. v8 is based on linux-next next-20220520 and Chen-Yu's series[1].
> 
> Changes for v7:
> 1. v7 is based on linux-next next-20220519 and Chen-Yu's series[1].
> 2. Add support for MT8186.
> 
> [1]: https://patchwork.kernel.org/project/linux-mediatek/list/?series=643003
> 
> Changes for v6:
> 1. Add a new patch to support inuput argument index mode.
> 2. Revise definition in reset.h to index.
> 
> Rex-BC Chen (19):
>    clk: mediatek: reset: Add reset.h
>    clk: mediatek: reset: Fix written reset bit offset
>    clk: mediatek: reset: Refine and reorder functions in reset.c
>    clk: mediatek: reset: Extract common drivers to update function
>    clk: mediatek: reset: Merge and revise reset register function
>    clk: mediatek: reset: Revise structure to control reset register
>    clk: mediatek: reset: Support nonsequence base offsets of reset
>      registers
>    clk: mediatek: reset: Support inuput argument index mode
>    clk: mediatek: reset: Change return type for clock reset register
>      function
>    clk: mediatek: reset: Add new register reset function with device
>    clk: mediatek: reset: Add reset support for simple probe
>    dt-bindings: arm: mediatek: Add #reset-cells property for
>      MT8192/MT8195
>    dt-bindings: reset: mediatek: Add infra_ao reset index for
>      MT8192/MT8195
>    clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195
>    arm64: dts: mediatek: Add infra #reset-cells property for MT8192
>    arm64: dts: mediatek: Add infra #reset-cells property for MT8195
>    dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186
>    dt-bindings: arm: mediatek: Add #reset-cells property for MT8186
>    clk: mediatek: reset: Add infra_ao reset support for MT8186
> 
>   .../mediatek/mediatek,mt8186-sys-clock.yaml   |   3 +
>   .../mediatek/mediatek,mt8192-sys-clock.yaml   |   3 +
>   .../mediatek/mediatek,mt8195-sys-clock.yaml   |   3 +
>   arch/arm64/boot/dts/mediatek/mt8192.dtsi      |   1 +
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi      |  15 +-
>   drivers/clk/mediatek/clk-mt2701-eth.c         |  10 +-
>   drivers/clk/mediatek/clk-mt2701-g3d.c         |  10 +-
>   drivers/clk/mediatek/clk-mt2701-hif.c         |  10 +-
>   drivers/clk/mediatek/clk-mt2701.c             |  22 +-
>   drivers/clk/mediatek/clk-mt2712.c             |  22 +-
>   drivers/clk/mediatek/clk-mt7622-eth.c         |  10 +-
>   drivers/clk/mediatek/clk-mt7622-hif.c         |  12 +-
>   drivers/clk/mediatek/clk-mt7622.c             |  22 +-
>   drivers/clk/mediatek/clk-mt7629-eth.c         |  10 +-
>   drivers/clk/mediatek/clk-mt7629-hif.c         |  12 +-
>   drivers/clk/mediatek/clk-mt8135.c             |  22 +-
>   drivers/clk/mediatek/clk-mt8173.c             |  22 +-
>   drivers/clk/mediatek/clk-mt8183.c             |  18 +-
>   drivers/clk/mediatek/clk-mt8186-infra_ao.c    |  23 ++
>   drivers/clk/mediatek/clk-mt8192.c             |  29 +++
>   drivers/clk/mediatek/clk-mt8195-infra_ao.c    |  24 +++
>   drivers/clk/mediatek/clk-mtk.c                |   7 +
>   drivers/clk/mediatek/clk-mtk.h                |   9 +-
>   drivers/clk/mediatek/reset.c                  | 198 +++++++++++++-----
>   drivers/clk/mediatek/reset.h                  |  82 ++++++++
>   include/dt-bindings/reset/mt8186-resets.h     |   5 +
>   include/dt-bindings/reset/mt8192-resets.h     |   8 +
>   include/dt-bindings/reset/mt8195-resets.h     |   6 +
>   28 files changed, 523 insertions(+), 95 deletions(-)
>   create mode 100644 drivers/clk/mediatek/reset.h
>

On Mon, 2022-05-23 at 17:33 +0800, Rex-BC Chen wrote:
> In this series, we cleanup MediaTek clock reset drivers in
> clk/mediatek
> folder. MediaTek clock reset driver is used to provide reset control
> of modules controlled in clk, like infra_ao.
> 
> Changes for v8 resend:
> 1. Remove tested-by tag from Nícolas for MT8195/MT8186 patches.
> 2. Add reviewed-by tag from AngeloGioacchino.
> 
> Changes for v8:
> 1. Use 'enum mtk_reset_version' to replace u8 in patch 5 and 6.
> 2. Use lowercase '0xc' in patch 7.
> 3. Drop "simple-mfd" in patch 16 because it's for original reset
> controller.
> 4. v8 is based on linux-next next-20220520 and Chen-Yu's series[1].
> 
> Changes for v7:
> 1. v7 is based on linux-next next-20220519 and Chen-Yu's series[1].
> 2. Add support for MT8186.
> 
> [1]: 
> https://patchwork.kernel.org/project/linux-mediatek/list/?series=643003
> 
> Changes for v6:
> 1. Add a new patch to support inuput argument index mode.
> 2. Revise definition in reset.h to index.
> 
> Rex-BC Chen (19):
>   clk: mediatek: reset: Add reset.h
>   clk: mediatek: reset: Fix written reset bit offset
>   clk: mediatek: reset: Refine and reorder functions in reset.c
>   clk: mediatek: reset: Extract common drivers to update function
>   clk: mediatek: reset: Merge and revise reset register function
>   clk: mediatek: reset: Revise structure to control reset register
>   clk: mediatek: reset: Support nonsequence base offsets of reset
>     registers
>   clk: mediatek: reset: Support inuput argument index mode
>   clk: mediatek: reset: Change return type for clock reset register
>     function
>   clk: mediatek: reset: Add new register reset function with device
>   clk: mediatek: reset: Add reset support for simple probe
>   dt-bindings: arm: mediatek: Add #reset-cells property for
>     MT8192/MT8195
>   dt-bindings: reset: mediatek: Add infra_ao reset index for
>     MT8192/MT8195
>   clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195
>   arm64: dts: mediatek: Add infra #reset-cells property for MT8192
>   arm64: dts: mediatek: Add infra #reset-cells property for MT8195
>   dt-bindings: reset: mediatek: Add infra_ao reset index for MT8186
>   dt-bindings: arm: mediatek: Add #reset-cells property for MT8186
>   clk: mediatek: reset: Add infra_ao reset support for MT8186
> 
>  .../mediatek/mediatek,mt8186-sys-clock.yaml   |   3 +
>  .../mediatek/mediatek,mt8192-sys-clock.yaml   |   3 +
>  .../mediatek/mediatek,mt8195-sys-clock.yaml   |   3 +
>  arch/arm64/boot/dts/mediatek/mt8192.dtsi      |   1 +
>  arch/arm64/boot/dts/mediatek/mt8195.dtsi      |  15 +-
>  drivers/clk/mediatek/clk-mt2701-eth.c         |  10 +-
>  drivers/clk/mediatek/clk-mt2701-g3d.c         |  10 +-
>  drivers/clk/mediatek/clk-mt2701-hif.c         |  10 +-
>  drivers/clk/mediatek/clk-mt2701.c             |  22 +-
>  drivers/clk/mediatek/clk-mt2712.c             |  22 +-
>  drivers/clk/mediatek/clk-mt7622-eth.c         |  10 +-
>  drivers/clk/mediatek/clk-mt7622-hif.c         |  12 +-
>  drivers/clk/mediatek/clk-mt7622.c             |  22 +-
>  drivers/clk/mediatek/clk-mt7629-eth.c         |  10 +-
>  drivers/clk/mediatek/clk-mt7629-hif.c         |  12 +-
>  drivers/clk/mediatek/clk-mt8135.c             |  22 +-
>  drivers/clk/mediatek/clk-mt8173.c             |  22 +-
>  drivers/clk/mediatek/clk-mt8183.c             |  18 +-
>  drivers/clk/mediatek/clk-mt8186-infra_ao.c    |  23 ++
>  drivers/clk/mediatek/clk-mt8192.c             |  29 +++
>  drivers/clk/mediatek/clk-mt8195-infra_ao.c    |  24 +++
>  drivers/clk/mediatek/clk-mtk.c                |   7 +
>  drivers/clk/mediatek/clk-mtk.h                |   9 +-
>  drivers/clk/mediatek/reset.c                  | 198 +++++++++++++---
> --
>  drivers/clk/mediatek/reset.h                  |  82 ++++++++
>  include/dt-bindings/reset/mt8186-resets.h     |   5 +
>  include/dt-bindings/reset/mt8192-resets.h     |   8 +
>  include/dt-bindings/reset/mt8195-resets.h     |   6 +
>  28 files changed, 523 insertions(+), 95 deletions(-)
>  create mode 100644 drivers/clk/mediatek/reset.h
> 

Hello Stephen,

Gentle ping for this series.
I also pushed another series to move these drivers to drivers/reset
folder[1], but I think we still can let this series merged.

If you have any comments for [1], please let me know.

Thanks.

[1]: 
https://patchwork.kernel.org/project/linux-mediatek/patch/20220527090355.7354-1-rex-bc.chen@mediatek.com/

BRs,
Bo-Chen

Quoting Rex-BC Chen (2022-05-23 02:33:28)
> Add a new file "reset.h" to place some definitions for clock reset.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---

Applied to clk-next

Quoting Rex-BC Chen (2022-05-23 02:33:29)
> Original assert/deassert bit is BIT(0), but it's more resonable to modify
> them to BIT(id % 32) which is based on id.
> 
> This patch will not influence any previous driver because the reset is
> only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0.
> 
> Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver")
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---

Applied to clk-next

Quoting Rex-BC Chen (2022-05-23 02:33:30)
> To make drivers more readable, we modify the indentation of the drivers
> and reorder the location of functions.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---

Applied to clk-next

Quoting Rex-BC Chen (2022-05-23 02:33:31)
> To make drivers more clear and readable, we extract common code
> within assert and deassert to mtk_reset_update_set_clr() and
> mtk_reset_update().
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---

Applied to clk-next

Quoting Rex-BC Chen (2022-05-23 02:33:32)
> There are two versions for clock reset register control for MediaTek
> SoCs. The old hardware is one bit per reset control, and does not
> have separate registers for bit set, clear and read-back operations.
> This matches the scheme supported by the simple reset driver.
> 
> However, because we need to use different data structure from
> reset_simple_data, we can not use the operation of simple reset
> driver.
> For this reason, we keep the original functions and name this version
> as "MTK_RST_SIMPLE".
> 
> In this patch:
> - Add a version enumeration to separate different reset hardware.
> - Merge the reset register function of simple and set_clr into one
>   function "mtk_register_reset_controller".
> - Rename input variable "num_regs" to "rst_bank_nr" to avoid
>   confusion. This variable is used to define the quantity of reset bank.
> - Document mtk_reset_version and mtk_register_reset_controller.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---

Applied to clk-next

Quoting Rex-BC Chen (2022-05-23 02:33:33)
> To declare the reset data easier, we add a strucure to do this instead
> of using many input variables to mtk_register_reset_controller().
> 
> - Add mtk_clk_rst_desc to define the reset description when registering
>   the reset controller.
> - Rename "mtk_reset" to "mtk_clk_rst_data". We use it to store data of
>   reset controller.
> - Document mtk_clk_rst_desc and mtk_clk_rst_data.
> - Modify the documentation of mtk_register_reset_controller.
> - Extract container_of in update functions to to_mtk_clk_rst_data().
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---

Applied to clk-next

Quoting Rex-BC Chen (2022-05-23 02:33:34)
> The bank offsets are not serial for all reset registers.
> For example, there are five infra reset banks for MT8192: 0x120, 0x130,
> 0x140, 0x150 and 0x730.
> 
> To support this,
> - Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of
>   the reset register.
> - Add a new define RST_NR_PER_BANK to define reset number for each
>   reset bank.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---

Applied to clk-next

Quoting Rex-BC Chen (2022-05-23 02:33:35)
> There is a large number of mediatek infra reset bits, but we do not use
> all of them. In addition, the proper input argement of reset controller
> soulde be index.
> Therefore, to be compatible with previous drivers and usage, we add
> description variables to store the ids which can mapping to index.
> 
> To use this mode, we need to put the id in rst_idx_map to map from
> index to ids. For example, if we want to input index 1 (this index
> is used to set bank 1 bit 14) for svs, we need to declare the reset
> controller like this:
> 
> In drivers:
> static u16 rst_ofs[] = {
>         0x120, 0x130, 0x140, 0x150, 0x730,
> };
> 
> static u16 rst_idx_map[] = {
>         0 * 32 + 0,
>         1 * 32 + 14,
>         ....
> };
> 
> static const struct mtk_clk_rst_desc clk_rst_desc = {
>         .version = MTK_RST_SET_CLR,
>         .rst_bank_ofs = rst_ofs,
>         .rst_bank_nr = ARRAY_SIZE(rst_ofs),
>         .rst_idx_map = rst_idx_map,
>         .rst_idx_map_nr = ARRAY_SIZE(rst_idx_map),
> };
> 
> In dts:
> svs: {
>         ...
>         resets = <&infra 1>;
>         ...
> };
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---

Applied to clk-next

Quoting Rex-BC Chen (2022-05-23 02:33:36)
> To deal with error handling, we change the function return type from
> void to int for mtk_clk_register_rst_ctrl().
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---

Applied to clk-next

Quoting Rex-BC Chen (2022-05-23 02:33:37)
> Using device to register reset controller is a better implementation in
> current drivers. Howerver, some clock drviers of MediaTek only provide
> device_node.
> 
> Therefore, we still remain the register reset function with device_node
> and add a new function with device to register reset controller.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---

Applied to clk-next

Quoting Rex-BC Chen (2022-05-23 02:33:38)
> - Add a pointer of "mtk_clk_rst_desc" to "mtk_clk_desc".
> - Add register reset with device function in mtk_clk_simple_probe().
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---

Applied to clk-next

Quoting Rex-BC Chen (2022-05-23 02:33:41)
> The infra_ao reset is needed for MT8192 and MT8195.
> - Add mtk_clk_rst_desc for MT8192 and MT8195
> - Add register reset controller function for MT8192 infra_ao.
> - Move definition of infra reset from cl-mt8183.c to reset.h
>   because it's the same definition with MT8192 and MT8195.
> - Add new definition of infra reset_4 for MT8192 and MT8195.
> - Add infra_ao_idx_map for MT8192 and MT8195.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> [Nícolas: Test for MT8192]
> Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> ---

Applied to clk-next

Quoting Rex-BC Chen (2022-05-23 02:33:46)
> The infra_ao reset is needed for MT8186.
> - Add mtk_clk_rst_desc for MT8186.
> - Add register reset controller function for MT8186 infra_ao.
> - Add infra_ao_idx_map for MT8186.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---

Applied to clk-next

Quoting Rex-BC Chen (2022-06-12 22:26:52)
> I also pushed another series to move these drivers to drivers/reset
> folder[1], but I think we still can let this series merged.

Sure. I merged everything except the DTS patches.

> 
> If you have any comments for [1], please let me know.

I'll take a look. Thanks.