Message ID | 70e4f5ae-e59a-d0ba-68b9-72d27de09c44@gmail.com |
---|---|
State | New |
Headers | show |
Series | [1/3,ARM] STAR-MC1 CPU Support - arm: Add star-mc1 core | expand |
Hi jasonwucj, > -----Original Message----- > From: Gcc-patches <gcc-patches- > bounces+kyrylo.tkachov=arm.com@gcc.gnu.org> On Behalf Of Chung-Ju Wu > via Gcc-patches > Sent: Thursday, May 26, 2022 8:18 AM > To: Richard Earnshaw <Richard.Earnshaw@arm.com>; gcc-patches <gcc- > patches@gcc.gnu.org> > Cc: Jason.Wu@anshingtek.com.tw > Subject: [PATCH 1/3][ARM] STAR-MC1 CPU Support - arm: Add star-mc1 core > > Hi, > > STAR-MC1 is an embedded processor with armv8m architecture. Majorly it > is designed to meet the requirements of AIoT application performance, > power consumption and security. Early this month, star-mc1 is supported by > the latest releases of MDK and CMSIS. For the completeness of Arm > ecosystem, > it would be great if we can have star-mc1 support in official GCC as well. > > Attached is the patch to support star-mc1 cpu in GCC: > > * Fundamental of -mcpu=star-mc1 option > - Based on latest upstream commit: > https://gcc.gnu.org/g:3dff965cae6709a5fd1b7b05c51c3c8aba786961 > - Add star-mc1 cpu in arm-cpus.in and regenerate necessary > implementation > > * Include VLLDM bugfix > - CVE-2021-35465 also affects star-mc1 configuration [1] > - We apply quirk_vlldm strategy for star-mc1 cpu > > Successfully bootstrapped and tested on arm-none-eabi. > > Is it OK for trunk? This is okay (together with the documentation additions in 3/3) Thanks for the patch, Kyrill > > [1] https://www.cve.org/CVERecord?id=CVE-2021-35465 > > Regards, > jasonwucj
Hi Kyrylo, On 2022/06/06 22:10 UTC+8, Kyrylo Tkachov wrote: >> >> Successfully bootstrapped and tested on arm-none-eabi. >> >> Is it OK for trunk? > > This is okay (together with the documentation additions in 3/3) > Thanks for the patch, Thanks for the approval. The patches 1/3 and 3/3 have been merged into one single patch and committed as: https://gcc.gnu.org/g:ef5cc6bbb60b0ccbc10fb76b697ae02f28af18c0 Regards, jasonwucj
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in index 0d3082b569f..5a63bc548e5 100644 --- a/gcc/config/arm/arm-cpus.in +++ b/gcc/config/arm/arm-cpus.in @@ -1638,6 +1638,16 @@ begin cpu cortex-m55 vendor 41 end cpu cortex-m55 +begin cpu star-mc1 + cname starmc1 + tune flags LDSCHED + architecture armv8-m.main+dsp+fp + option nofp remove ALL_FP + option nodsp remove armv7em + isa quirk_no_asmcpu quirk_vlldm + costs v7m +end cpu star-mc1 + # V8 R-profile implementations. begin cpu cortex-r52 cname cortexr52 diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index ef0cc5ef0c8..e6461abcc57 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -282,6 +282,9 @@ Enum(processor_type) String(cortex-m35p) Value( TARGET_CPU_cortexm35p) EnumValue Enum(processor_type) String(cortex-m55) Value( TARGET_CPU_cortexm55) +EnumValue +Enum(processor_type) String(star-mc1) Value( TARGET_CPU_starmc1) + EnumValue Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52) diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 34225536042..abc290edd09 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -49,6 +49,6 @@ cortexa710,cortexx1,neoversen1, cortexa75cortexa55,cortexa76cortexa55,neoversev1, neoversen2,cortexm23,cortexm33, - cortexm35p,cortexm55,cortexr52, - cortexr52plus" + cortexm35p,cortexm55,starmc1, + cortexr52,cortexr52plus" (const (symbol_ref "((enum attr_tune) arm_tune)")))