| Message ID | 20220511150117.113070-1-pgwipeout@gmail.com |
|---|---|
| Headers | show |
| Series | Cleanups and enablement for Quartz64-A | expand |
On Wed, 11 May 2022 11:01:11 -0400, Peter Geis wrote: > Good Morning, > > The following patches clean up some dtbs_check warnings, fixup the > Quartz64-A dts, and enable some additional functionality on the > Quartz64-A. > > With this series the only remaining dtbs_check warnings are due to > unconverted bindings. > > [...] Applied, thanks! [1/6] dt-binding: clock: Add missing rk3568 cru bindings commit: b21445db9818ccb9fa1c0ba81fd3705eb8d347e3 [2/6] arm64: dts: rockchip: add clocks to rk356x cru commit: 70f679ad25d5f8d0076e283bd6c61e047c7af226 [3/6] arm64: dts: rockchip: rename Quartz64-A bluetooth gpios commit: 650a1523756bb1e697f8927d2915cbbb92e83f8c [4/6] arm64: dts: rockchip: add Quartz64-A fan pinctrl commit: 82f4f0183e5d3b2d0a2af6c70ba16f86b5897ef9 [5/6] arm64: dts: rockchip: enable sdr-104 on sdmmc commit: 6adce30701c810e11685911ca2114fbc0107120d [6/6] arm64: dts: rockchip: enable sfc controller on Quartz64 Model A commit: e5008be69a1947d4236ab3f73c939f9c2a9a6f80 Best regards,
On Wed, May 11, 2022 at 11:01:17AM -0400, Peter Geis wrote: > Add the sfc controller binding for the Quartz64 Model A. This is not > populated by default, so leave it disabled. > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > --- > .../boot/dts/rockchip/rk3566-quartz64-a.dts | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > index 71df64655de5..6ec349e7e521 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > @@ -603,6 +603,22 @@ &sdmmc1 { > status = "okay"; > }; > > +&sfc { > + pinctrl-0 = <&fspi_pins>; > + pinctrl-names = "default"; > + #address-cells = <1>; > + #size-cells = <0>; > + status = "disabled"; > + > + flash@0 { > + compatible = "jedec,spi-nor"; > + reg = <0>; > + spi-max-frequency = <24000000>; > + spi-rx-bus-width = <4>; > + spi-tx-bus-width = <1>; This isn't really a concern, just a comment. Did you test this with the spi-tx-bus-width of 4 by chance? While I did have to use 1 for my implementation (the Odroid Go Advance) the Rockchip engineer I worked with couldn't replicate the issue on his end and we ended up chalking my issues up to an implementation specific problem. I'm only commenting here because I don't want you to think that for this device the tx always has to be 1, of course if your implementation does have issues with a tx of 2 or 4 that's different... Thank you. > + }; > +}; > + > /* spdif is exposed on con40 pin 18 */ > &spdif { > status = "okay"; > -- > 2.25.1 >
On Mon, May 16, 2022 at 11:26 AM Chris Morgan <macroalpha82@gmail.com> wrote: > > On Wed, May 11, 2022 at 11:01:17AM -0400, Peter Geis wrote: > > Add the sfc controller binding for the Quartz64 Model A. This is not > > populated by default, so leave it disabled. > > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com> > > --- > > .../boot/dts/rockchip/rk3566-quartz64-a.dts | 16 ++++++++++++++++ > > 1 file changed, 16 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > index 71df64655de5..6ec349e7e521 100644 > > --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts > > @@ -603,6 +603,22 @@ &sdmmc1 { > > status = "okay"; > > }; > > > > +&sfc { > > + pinctrl-0 = <&fspi_pins>; > > + pinctrl-names = "default"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + status = "disabled"; > > + > > + flash@0 { > > + compatible = "jedec,spi-nor"; > > + reg = <0>; > > + spi-max-frequency = <24000000>; > > + spi-rx-bus-width = <4>; > > + spi-tx-bus-width = <1>; > > This isn't really a concern, just a comment. Did you test this with the > spi-tx-bus-width of 4 by chance? While I did have to use 1 for my > implementation (the Odroid Go Advance) the Rockchip engineer I worked > with couldn't replicate the issue on his end and we ended up chalking > my issues up to an implementation specific problem. I'm only commenting > here because I don't want you to think that for this device the tx > always has to be 1, of course if your implementation does have issues > with a tx of 2 or 4 that's different... Yes, and it was a data disaster. Looking into it I found all of the flash chips that I could find only support 4x RX 1x TX. Some didn't handle 4x RX terribly well either. > > Thank you. > > > + }; > > +}; > > + > > /* spdif is exposed on con40 pin 18 */ > > &spdif { > > status = "okay"; > > -- > > 2.25.1 > >