[V4,00/15] Cleanup MediaTek clk reset drivers and support MT8192/MT8195

In this series, we cleanup MediaTek clock reset drivers in clk/mediatek
folder. MediaTek clock reset driver is used to provide reset control
of modules controlled in clk, like infra_ao.

Changes for V4:
1. Abandon the implementation of reset-cell = 2, and use reset index to
   determine which reset bit is used.
2. Add documentation for enum/structure/function in reset.h.
3. Combine binding/drvier support patch for MT8192 and MT8195.
4. The MT8195 DTS is accepted by Matthias, and I add new DTS patch to
   support infracfg_ao reset for MT8195. The DTS of MT8195 is still
   not merged into mainline. Please refer to [1].

[1]: https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/commit/?h=for-next&id=37f2582883be7218dc69f9af135959a8e93de223

Changes for V3:
1. Modify drivers for reviewers' comments.
2. Add dt-binding patch for MT8192/MT8195 infra.
3. Add reset property of infra node for MT8192.
4. Use original function for simple operation.

Changes for V2:
1. Modify drivers for reviewers' comments.
2. Use simple reset to replace v1.
3. Recover v2 to set_clr.
4. Separate error handling to another patch.
5. Add support for input offset and bit from DT.
6. Add support for MT8192 and MT8195.

Rex-BC Chen (15):
  clk: mediatek: reset: Add reset.h
  clk: mediatek: reset: Fix written reset bit offset
  clk: mediatek: reset: Refine and reorder functions in reset.c
  clk: mediatek: reset: Extract common drivers to update function
  clk: mediatek: reset: Merge and revise reset register function
  clk: mediatek: reset: Revise structure to control reset register
  clk: mediatek: reset: Support nonsequence base offsets of reset registers
  clk: mediatek: reset: Change return type for clock reset register function
  clk: mediatek: reset: Add new register reset function with device
  clk: mediatek: reset: Add reset support for simple probe
  dt-bindings: arm: mediatek: Add #reset-cells property for MT8192/MT8195
  dt-bindings: reset: mediatek: Add infra_ao reset bit for MT8192/MT8195
  clk: mediatek: reset: Add infra_ao reset support for MT8192/MT8195
  arm64: dts: mediatek: Add infra #reset-cells property for MT8192
  arm64: dts: mediatek: Add infra #reset-cells property for MT8195

 .../mediatek/mediatek,mt8192-sys-clock.yaml   |   3 +
 .../mediatek/mediatek,mt8195-sys-clock.yaml   |   3 +
 arch/arm64/boot/dts/mediatek/mt8192.dtsi      |   1 +
 arch/arm64/boot/dts/mediatek/mt8195.dtsi      |  13 +-
 drivers/clk/mediatek/clk-mt2701-eth.c         |  10 +-
 drivers/clk/mediatek/clk-mt2701-g3d.c         |  10 +-
 drivers/clk/mediatek/clk-mt2701-hif.c         |  10 +-
 drivers/clk/mediatek/clk-mt2701.c             |  22 ++-
 drivers/clk/mediatek/clk-mt2712.c             |  22 ++-
 drivers/clk/mediatek/clk-mt7622-eth.c         |  10 +-
 drivers/clk/mediatek/clk-mt7622-hif.c         |  12 +-
 drivers/clk/mediatek/clk-mt7622.c             |  22 ++-
 drivers/clk/mediatek/clk-mt7629-eth.c         |  10 +-
 drivers/clk/mediatek/clk-mt7629-hif.c         |  12 +-
 drivers/clk/mediatek/clk-mt8135.c             |  22 ++-
 drivers/clk/mediatek/clk-mt8173.c             |  22 ++-
 drivers/clk/mediatek/clk-mt8183.c             |  18 +-
 drivers/clk/mediatek/clk-mt8192.c             |  18 ++
 drivers/clk/mediatek/clk-mt8195-infra_ao.c    |  15 ++
 drivers/clk/mediatek/clk-mtk.c                |   7 +
 drivers/clk/mediatek/clk-mtk.h                |   9 +-
 drivers/clk/mediatek/reset.c                  | 172 ++++++++++++------
 drivers/clk/mediatek/reset.h                  |  77 ++++++++
 include/dt-bindings/reset/mt8192-resets.h     |   8 +
 include/dt-bindings/reset/mt8195-resets.h     |   6 +
 25 files changed, 440 insertions(+), 94 deletions(-)
 create mode 100644 drivers/clk/mediatek/reset.h

Il 27/04/22 05:09, Rex-BC Chen ha scritto:
> The bank offsets are not serial for all reset registers.
> For example, there are five infra reset banks for MT8192: 0x120, 0x130,
> 0x140, 0x150 and 0x730.
> 
> To support this,
> - Change reg_ofs to rst_bank_ofs which is a pointer to base offsets of
>    the reset register.
> - Add a new define RST_NR_PER_BANK to define reset number for each
>    reset bank.
> 
> Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> ---
>   drivers/clk/mediatek/clk-mt2701-eth.c |  6 ++++--
>   drivers/clk/mediatek/clk-mt2701-g3d.c |  6 ++++--
>   drivers/clk/mediatek/clk-mt2701-hif.c |  6 ++++--
>   drivers/clk/mediatek/clk-mt2701.c     | 11 +++++++----
>   drivers/clk/mediatek/clk-mt2712.c     | 15 +++++++++------
>   drivers/clk/mediatek/clk-mt7622-eth.c |  6 ++++--
>   drivers/clk/mediatek/clk-mt7622-hif.c |  6 ++++--
>   drivers/clk/mediatek/clk-mt7622.c     | 11 +++++++----
>   drivers/clk/mediatek/clk-mt7629-eth.c |  6 ++++--
>   drivers/clk/mediatek/clk-mt7629-hif.c |  6 ++++--
>   drivers/clk/mediatek/clk-mt8135.c     | 11 +++++++----
>   drivers/clk/mediatek/clk-mt8173.c     | 11 +++++++----
>   drivers/clk/mediatek/clk-mt8183.c     | 14 ++++++++++++--
>   drivers/clk/mediatek/reset.c          | 11 ++++++-----
>   drivers/clk/mediatek/reset.h          |  6 ++++--
>   15 files changed, 87 insertions(+), 45 deletions(-)
> 

..snip..

> diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
> index 70a934faa529..ebb1b9975ab0 100644
> --- a/drivers/clk/mediatek/clk-mt2701.c
> +++ b/drivers/clk/mediatek/clk-mt2701.c
> @@ -735,18 +735,21 @@ static const struct mtk_fixed_factor infra_fixed_divs[] = {
>   	FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
>   };
>   
> +static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
> +static u16 perfcfg_rst_ofs[] = { 0x0, 0x4, };

Typo: perfcfg -> pericfg ... here and in some more files :))

> +
>   static const struct mtk_clk_rst_desc clk_rst_desc[] = {
>   	/* infrasys */
>   	{
>   		.version = MTK_RST_SIMPLE,
> -		.rst_bank_nr = 2,
> -		.reg_ofs = 0x30,
> +		.rst_bank_ofs = infrasys_rst_ofs,
> +		.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
>   	},
>   	/* pericfg */
>   	{
>   		.version = MTK_RST_SIMPLE,
> -		.rst_bank_nr = 2,
> -		.reg_ofs = 0x0,
> +		.rst_bank_ofs = perfcfg_rst_ofs,
> +		.rst_bank_nr = ARRAY_SIZE(perfcfg_rst_ofs),
>   	},
>   };
>   
> diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
> index cef7c79788ec..2a9d70dd97d6 100644
> --- a/drivers/clk/mediatek/clk-mt2712.c
> +++ b/drivers/clk/mediatek/clk-mt2712.c
> @@ -1258,18 +1258,21 @@ static const struct mtk_pll_data plls[] = {
>   		0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
>   };
>   
> +static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
> +static u16 perfcfg_rst_ofs[] = { 0x0, 0x4, };
> +
>   static const struct mtk_clk_rst_desc clk_rst_desc[] = {
> -	/* infra */
> +	/* infrasys */

Instead of renaming these here, if you really want this renamed, can you please
do that in patch [06/15]?

>   	{
>   		.version = MTK_RST_SIMPLE,
> -		.rst_bank_nr = 2,
> -		.reg_ofs = 0x30,
> +		.rst_bank_ofs = infrasys_rst_ofs,
> +		.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
>   	},

..snip..

> diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
> index 91358e8cb851..83840ecf8b27 100644
> --- a/drivers/clk/mediatek/reset.h
> +++ b/drivers/clk/mediatek/reset.h
> @@ -9,6 +9,8 @@
>   #include <linux/reset-controller.h>
>   #include <linux/types.h>
>   
> +#define RST_NR_PER_BANK 32
> +
>   /**
>    * enum mtk_reset_version - Version of MediaTek clock reset controller.
>    * @MTK_RST_SIMPLE: Use the same registers for bit set and clear.
> @@ -24,12 +26,12 @@ enum mtk_reset_version {
>   /**
>    * struct mtk_clk_rst_desc - Description of MediaTek clock reset.
>    * @version: Reset version which is defined in enum mtk_reset_version.
> - * @reg_ofs: Base offset of the reset register.
> + * @rst_bank_ofs: Pointer to base offsets of the reset register.

Instead of generically saying that this is a pointer, it would be more
appropriate to say that this is a pointer to an array containing base
offsets (etc).

Thanks,
Angelo

>    * @rst_bank_nr: Quantity of reset bank.
>    */
>   struct mtk_clk_rst_desc {
>   	u8 version;
> -	u16 reg_ofs;
> +	u16 *rst_bank_ofs;
>   	u32 rst_bank_nr;
>   };
>

On Wed, 2022-04-27 at 15:38 +0200, AngeloGioacchino Del Regno wrote:
> Il 27/04/22 05:09, Rex-BC Chen ha scritto:
> > The bank offsets are not serial for all reset registers.
> > For example, there are five infra reset banks for MT8192: 0x120,
> > 0x130,
> > 0x140, 0x150 and 0x730.
> > 
> > To support this,
> > - Change reg_ofs to rst_bank_ofs which is a pointer to base offsets
> > of
> >    the reset register.
> > - Add a new define RST_NR_PER_BANK to define reset number for each
> >    reset bank.
> > 
> > Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
> > ---
> >   drivers/clk/mediatek/clk-mt2701-eth.c |  6 ++++--
> >   drivers/clk/mediatek/clk-mt2701-g3d.c |  6 ++++--
> >   drivers/clk/mediatek/clk-mt2701-hif.c |  6 ++++--
> >   drivers/clk/mediatek/clk-mt2701.c     | 11 +++++++----
> >   drivers/clk/mediatek/clk-mt2712.c     | 15 +++++++++------
> >   drivers/clk/mediatek/clk-mt7622-eth.c |  6 ++++--
> >   drivers/clk/mediatek/clk-mt7622-hif.c |  6 ++++--
> >   drivers/clk/mediatek/clk-mt7622.c     | 11 +++++++----
> >   drivers/clk/mediatek/clk-mt7629-eth.c |  6 ++++--
> >   drivers/clk/mediatek/clk-mt7629-hif.c |  6 ++++--
> >   drivers/clk/mediatek/clk-mt8135.c     | 11 +++++++----
> >   drivers/clk/mediatek/clk-mt8173.c     | 11 +++++++----
> >   drivers/clk/mediatek/clk-mt8183.c     | 14 ++++++++++++--
> >   drivers/clk/mediatek/reset.c          | 11 ++++++-----
> >   drivers/clk/mediatek/reset.h          |  6 ++++--
> >   15 files changed, 87 insertions(+), 45 deletions(-)
> > 
> 
> ..snip..
> 
> > diff --git a/drivers/clk/mediatek/clk-mt2701.c
> > b/drivers/clk/mediatek/clk-mt2701.c
> > index 70a934faa529..ebb1b9975ab0 100644
> > --- a/drivers/clk/mediatek/clk-mt2701.c
> > +++ b/drivers/clk/mediatek/clk-mt2701.c
> > @@ -735,18 +735,21 @@ static const struct mtk_fixed_factor
> > infra_fixed_divs[] = {
> >   	FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
> >   };
> >   
> > +static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
> > +static u16 perfcfg_rst_ofs[] = { 0x0, 0x4, };
> 
> Typo: perfcfg -> pericfg ... here and in some more files :))
> 

Hello Angelo,

Thanks for your review!

I will fix them.

> > +
> >   static const struct mtk_clk_rst_desc clk_rst_desc[] = {
> >   	/* infrasys */
> >   	{
> >   		.version = MTK_RST_SIMPLE,
> > -		.rst_bank_nr = 2,
> > -		.reg_ofs = 0x30,
> > +		.rst_bank_ofs = infrasys_rst_ofs,
> > +		.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
> >   	},
> >   	/* pericfg */
> >   	{
> >   		.version = MTK_RST_SIMPLE,
> > -		.rst_bank_nr = 2,
> > -		.reg_ofs = 0x0,
> > +		.rst_bank_ofs = perfcfg_rst_ofs,
> > +		.rst_bank_nr = ARRAY_SIZE(perfcfg_rst_ofs),
> >   	},
> >   };
> >   
> > diff --git a/drivers/clk/mediatek/clk-mt2712.c
> > b/drivers/clk/mediatek/clk-mt2712.c
> > index cef7c79788ec..2a9d70dd97d6 100644
> > --- a/drivers/clk/mediatek/clk-mt2712.c
> > +++ b/drivers/clk/mediatek/clk-mt2712.c
> > @@ -1258,18 +1258,21 @@ static const struct mtk_pll_data plls[] = {
> >   		0, 31, 0x0300, 4, 0, 0, 0, 0x0304, 0),
> >   };
> >   
> > +static u16 infrasys_rst_ofs[] = { 0x30, 0x34, };
> > +static u16 perfcfg_rst_ofs[] = { 0x0, 0x4, };
> > +
> >   static const struct mtk_clk_rst_desc clk_rst_desc[] = {
> > -	/* infra */
> > +	/* infrasys */
> 
> Instead of renaming these here, if you really want this renamed, can
> you please
> do that in patch [06/15]?
> 

I will remove them.

> >   	{
> >   		.version = MTK_RST_SIMPLE,
> > -		.rst_bank_nr = 2,
> > -		.reg_ofs = 0x30,
> > +		.rst_bank_ofs = infrasys_rst_ofs,
> > +		.rst_bank_nr = ARRAY_SIZE(infrasys_rst_ofs),
> >   	},
> 
> ..snip..
> 
> > diff --git a/drivers/clk/mediatek/reset.h
> > b/drivers/clk/mediatek/reset.h
> > index 91358e8cb851..83840ecf8b27 100644
> > --- a/drivers/clk/mediatek/reset.h
> > +++ b/drivers/clk/mediatek/reset.h
> > @@ -9,6 +9,8 @@
> >   #include <linux/reset-controller.h>
> >   #include <linux/types.h>
> >   
> > +#define RST_NR_PER_BANK 32
> > +
> >   /**
> >    * enum mtk_reset_version - Version of MediaTek clock reset
> > controller.
> >    * @MTK_RST_SIMPLE: Use the same registers for bit set and clear.
> > @@ -24,12 +26,12 @@ enum mtk_reset_version {
> >   /**
> >    * struct mtk_clk_rst_desc - Description of MediaTek clock reset.
> >    * @version: Reset version which is defined in enum
> > mtk_reset_version.
> > - * @reg_ofs: Base offset of the reset register.
> > + * @rst_bank_ofs: Pointer to base offsets of the reset register.
> 
> Instead of generically saying that this is a pointer, it would be
> more
> appropriate to say that this is a pointer to an array containing base
> offsets (etc).
> 

ok, I will modify it.

BRs,
Rex

> Thanks,
> Angelo
> 
> >    * @rst_bank_nr: Quantity of reset bank.
> >    */
> >   struct mtk_clk_rst_desc {
> >   	u8 version;
> > -	u16 reg_ofs;
> > +	u16 *rst_bank_ofs;
> >   	u32 rst_bank_nr;
> >   };
> >