[v6,0/4] Enable rk356x PCIe controller

This series enables the DesignWare based PCIe controller on the rk356x
series of chips.
We drop the fallback to the core driver due to compatibility issues.
We add support for legacy interrupts for cards that lack MSI support
(which is partially broken currently).
We then add the device tree nodes to enable PCIe on the Quartz64 Model
A.

Patch 1 drops the snps,dw,pcie fallback from the dt-binding
Patch 2 adds legacy interrupt support to the driver
Patch 3 adds the device tree binding to the rk356x.dtsi
Patch 4 enables the PCIe controller on the Quartz64-A

Changelog:
v6:
- fix a ranges issue
- point to gic instead of its

v5:
- fix incorrect series (apologies for the v4 spam)

v4:
- drop the ITS modification, poor compatibility is better than
  completely broken

v3:
- drop select node from dt-binding
- convert to for_each_set_bit
- convert to generic_handle_domain_irq
- drop unncessary dev_err
- reorder irq_chip items
- change to level_irq
- install the handler after initializing the domain

v2:
- Define PCIE_CLIENT_INTR_STATUS_LEGACY
- Fix PCIE_LEGACY_INT_ENABLE to only enable the RC interrupts
- Add legacy interrupt enable/disable support

Peter Geis (4):
  dt-bindings: pci: remove fallback from Rockchip DesignWare binding
  PCI: dwc: rockchip: add legacy interrupt support
  arm64: dts: rockchip: add rk3568 pcie2x1 controller
  arm64: dts: rockchip: enable pcie controller on quartz64-a

 .../bindings/pci/rockchip-dw-pcie.yaml        |  12 +-
 .../boot/dts/rockchip/rk3566-quartz64-a.dts   |  34 ++++++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      |  55 +++++++++
 drivers/pci/controller/dwc/pcie-dw-rockchip.c | 112 +++++++++++++++++-
 4 files changed, 200 insertions(+), 13 deletions(-)

Hi Peter,

On 4/16/22 13:05, Peter Geis wrote:
> +	pcie2x1: pcie@fe260000 {
> +		compatible = "rockchip,rk3568-pcie";
> +		#address-cells = <3>;
> +		#size-cells = <2>;
> +		bus-range = <0x0 0xf>;
> +		assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
> +			 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
> +			 <&cru CLK_PCIE20_AUX_NDFT>;

Why these assigned-clocks are needed? I don't see anything assigned in
this patchset.

On Sat, Apr 16, 2022 at 6:08 AM Dmitry Osipenko
<dmitry.osipenko@collabora.com> wrote:
>
> Hi Peter,
>
> On 4/16/22 13:05, Peter Geis wrote:
> > +     pcie2x1: pcie@fe260000 {
> > +             compatible = "rockchip,rk3568-pcie";
> > +             #address-cells = <3>;
> > +             #size-cells = <2>;
> > +             bus-range = <0x0 0xf>;
> > +             assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
> > +                      <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
> > +                      <&cru CLK_PCIE20_AUX_NDFT>;
>
> Why these assigned-clocks are needed? I don't see anything assigned in
> this patchset.

Ah, those are remnants of early bringup when performance wasn't good
and I was manually setting clock rates.

On 4/16/22 13:17, Peter Geis wrote:
> On Sat, Apr 16, 2022 at 6:08 AM Dmitry Osipenko
> <dmitry.osipenko@collabora.com> wrote:
>>
>> Hi Peter,
>>
>> On 4/16/22 13:05, Peter Geis wrote:
>>> +     pcie2x1: pcie@fe260000 {
>>> +             compatible = "rockchip,rk3568-pcie";
>>> +             #address-cells = <3>;
>>> +             #size-cells = <2>;
>>> +             bus-range = <0x0 0xf>;
>>> +             assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
>>> +                      <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
>>> +                      <&cru CLK_PCIE20_AUX_NDFT>;
>>
>> Why these assigned-clocks are needed? I don't see anything assigned in
>> this patchset.
> 
> Ah, those are remnants of early bringup when performance wasn't good
> and I was manually setting clock rates.

If it's not needed, should it be removed then? Otherwise it looks like
something is missing in the DT in regards to the assigned clocks.

On Sun, Apr 17, 2022 at 6:23 PM Dmitry Osipenko
<dmitry.osipenko@collabora.com> wrote:
>
> On 4/16/22 13:17, Peter Geis wrote:
> > On Sat, Apr 16, 2022 at 6:08 AM Dmitry Osipenko
> > <dmitry.osipenko@collabora.com> wrote:
> >>
> >> Hi Peter,
> >>
> >> On 4/16/22 13:05, Peter Geis wrote:
> >>> +     pcie2x1: pcie@fe260000 {
> >>> +             compatible = "rockchip,rk3568-pcie";
> >>> +             #address-cells = <3>;
> >>> +             #size-cells = <2>;
> >>> +             bus-range = <0x0 0xf>;
> >>> +             assigned-clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
> >>> +                      <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
> >>> +                      <&cru CLK_PCIE20_AUX_NDFT>;
> >>
> >> Why these assigned-clocks are needed? I don't see anything assigned in
> >> this patchset.
> >
> > Ah, those are remnants of early bringup when performance wasn't good
> > and I was manually setting clock rates.
>
> If it's not needed, should it be removed then? Otherwise it looks like
> something is missing in the DT in regards to the assigned clocks.

Yes, it has been removed from the V7.
Thanks!