| Message ID | 20220329112935.10785-1-j@jannau.net |
|---|---|
| State | Accepted |
| Commit | 585fc1c8c535380e1ace681e34bb1e3c9e8bc7ae |
| Delegated to: | Tom Rini |
| Headers | show |
| Series | [1/1] arm: apple: Add M1 Ultra support | expand |
> From: Janne Grunau <j@jannau.net> > Date: Tue, 29 Mar 2022 13:29:35 +0200 > > The M1 Ultra consists of two M1 Max dies. The second die's I/O is at > a consistent offset of 0x2000000000. > > Signed-off-by: Janne Grunau <j@jannau.net> I think that's the way to do it. Technically we could probably get away with mapping the decond die's I/O even on single-die M1 Pro and M1 Max SoCs even if the hardware doesn't respond to access to those addresses since these are mapped as device memory. But that might be confusing and we don't really have any space constraints on these systems. Reviewed-by: Mark Kettenis <kettenis@openbsd.org> However, you should also update the documentation to indicate M1 Ultra support. See doc/board/apple/m1.rst > --- > arch/arm/mach-apple/board.c | 167 ++++++++++++++++++++++++++++++++++++ > 1 file changed, 167 insertions(+) > > diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c > index 722dff1f64c5..ffc1301cf57f 100644 > --- a/arch/arm/mach-apple/board.c > +++ b/arch/arm/mach-apple/board.c > @@ -177,6 +177,171 @@ static struct mm_region t6000_mem_map[] = { > } > }; > > +/* Apple M1 Ultra */ > + > +static struct mm_region t6002_mem_map[] = { > + { > + /* I/O */ > + .virt = 0x280000000, > + .phys = 0x280000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x380000000, > + .phys = 0x380000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x580000000, > + .phys = 0x580000000, > + .size = SZ_512M, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* PCIE */ > + .virt = 0x5a0000000, > + .phys = 0x5a0000000, > + .size = SZ_512M, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | > + PTE_BLOCK_INNER_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* PCIE */ > + .virt = 0x5c0000000, > + .phys = 0x5c0000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | > + PTE_BLOCK_INNER_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x700000000, > + .phys = 0x700000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0xb00000000, > + .phys = 0xb00000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0xf00000000, > + .phys = 0xf00000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x1300000000, > + .phys = 0x1300000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x2280000000, > + .phys = 0x2280000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x2380000000, > + .phys = 0x2380000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x2580000000, > + .phys = 0x2580000000, > + .size = SZ_512M, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* PCIE */ > + .virt = 0x25a0000000, > + .phys = 0x25a0000000, > + .size = SZ_512M, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | > + PTE_BLOCK_INNER_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* PCIE */ > + .virt = 0x25c0000000, > + .phys = 0x25c0000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | > + PTE_BLOCK_INNER_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x2700000000, > + .phys = 0x2700000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x2b00000000, > + .phys = 0x2b00000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x2f00000000, > + .phys = 0x2f00000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* I/O */ > + .virt = 0x3300000000, > + .phys = 0x3300000000, > + .size = SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | > + PTE_BLOCK_NON_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* RAM */ > + .virt = 0x10000000000, > + .phys = 0x10000000000, > + .size = 16UL * SZ_1G, > + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | > + PTE_BLOCK_INNER_SHARE > + }, { > + /* Framebuffer */ > + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | > + PTE_BLOCK_INNER_SHARE | > + PTE_BLOCK_PXN | PTE_BLOCK_UXN > + }, { > + /* List terminator */ > + 0, > + } > +}; > + > struct mm_region *mem_map; > > int board_init(void) > @@ -216,6 +381,8 @@ void build_mem_map(void) > mem_map = t6000_mem_map; > else if (of_machine_is_compatible("apple,t6001")) > mem_map = t6000_mem_map; > + else if (of_machine_is_compatible("apple,t6002")) > + mem_map = t6002_mem_map; > else > panic("Unsupported SoC\n"); > > -- > 2.35.1 > >
On Tue, Mar 29, 2022 at 01:29:35PM +0200, Janne Grunau wrote: > The M1 Ultra consists of two M1 Max dies. The second die's I/O is at > a consistent offset of 0x2000000000. > > Signed-off-by: Janne Grunau <j@jannau.net> > Reviewed-by: Mark Kettenis <kettenis@openbsd.org> Applied to u-boot/master, thanks!
> Date: Fri, 15 Apr 2022 08:06:56 -0400 > From: Tom Rini <trini@konsulko.com> > > On Tue, Mar 29, 2022 at 01:29:35PM +0200, Janne Grunau wrote: > > > The M1 Ultra consists of two M1 Max dies. The second die's I/O is at > > a consistent offset of 0x2000000000. > > > > Signed-off-by: Janne Grunau <j@jannau.net> > > Reviewed-by: Mark Kettenis <kettenis@openbsd.org> > > Applied to u-boot/master, thanks! Thanks Tom, That reminded me that owed you the documentation update that I just sent to the list.
diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c index 722dff1f64c5..ffc1301cf57f 100644 --- a/arch/arm/mach-apple/board.c +++ b/arch/arm/mach-apple/board.c @@ -177,6 +177,171 @@ static struct mm_region t6000_mem_map[] = { } }; +/* Apple M1 Ultra */ + +static struct mm_region t6002_mem_map[] = { + { + /* I/O */ + .virt = 0x280000000, + .phys = 0x280000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x380000000, + .phys = 0x380000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x580000000, + .phys = 0x580000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5a0000000, + .phys = 0x5a0000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x5c0000000, + .phys = 0x5c0000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x700000000, + .phys = 0x700000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0xb00000000, + .phys = 0xb00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0xf00000000, + .phys = 0xf00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x1300000000, + .phys = 0x1300000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2280000000, + .phys = 0x2280000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2380000000, + .phys = 0x2380000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2580000000, + .phys = 0x2580000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x25a0000000, + .phys = 0x25a0000000, + .size = SZ_512M, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* PCIE */ + .virt = 0x25c0000000, + .phys = 0x25c0000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRE) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2700000000, + .phys = 0x2700000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2b00000000, + .phys = 0x2b00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x2f00000000, + .phys = 0x2f00000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* I/O */ + .virt = 0x3300000000, + .phys = 0x3300000000, + .size = SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* RAM */ + .virt = 0x10000000000, + .phys = 0x10000000000, + .size = 16UL * SZ_1G, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* Framebuffer */ + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL_NC) | + PTE_BLOCK_INNER_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + struct mm_region *mem_map; int board_init(void) @@ -216,6 +381,8 @@ void build_mem_map(void) mem_map = t6000_mem_map; else if (of_machine_is_compatible("apple,t6001")) mem_map = t6000_mem_map; + else if (of_machine_is_compatible("apple,t6002")) + mem_map = t6002_mem_map; else panic("Unsupported SoC\n");
The M1 Ultra consists of two M1 Max dies. The second die's I/O is at a consistent offset of 0x2000000000. Signed-off-by: Janne Grunau <j@jannau.net> --- arch/arm/mach-apple/board.c | 167 ++++++++++++++++++++++++++++++++++++ 1 file changed, 167 insertions(+)