diff mbox series

[aarch64] Update Neoverse N2 core definition

Message ID 10661a9d-4031-fa1d-fd2f-667c8bdc529a@arm.com
State New
Headers show
Series [aarch64] Update Neoverse N2 core definition | expand

Commit Message

Andre Vieira (lists) March 16, 2022, 3 p.m. UTC 
Hi,

As requested, I updated the Neoverse N2 entry to use the 
AARCH64_FL_FOR_ARCH9 feature set, removed duplicate entries, updated the 
ARCH_INDENT to 9A and moved it under the Armv9 cores.

gcc/ChangeLog:

         * config/aarch64/aarch64-cores.def: Update Neoverse N2 core entry.

Comments

Andre Vieira (lists) March 24, 2022, 6:04 p.m. UTC | #1 
Ping.

On 16/03/2022 15:00, Andre Vieira (lists) via Gcc-patches wrote:
> Hi,
>
> As requested, I updated the Neoverse N2 entry to use the 
> AARCH64_FL_FOR_ARCH9 feature set, removed duplicate entries, updated 
> the ARCH_INDENT to 9A and moved it under the Armv9 cores.
>
> gcc/ChangeLog:
>
>         * config/aarch64/aarch64-cores.def: Update Neoverse N2 core 
> entry.
Kyrylo Tkachov March 25, 2022, 1:09 p.m. UTC | #2 
> -----Original Message-----
> From: Andre Vieira (lists) <andre.simoesdiasvieira@arm.com>
> Sent: Wednesday, March 16, 2022 3:01 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>; Richard Sandiford
> <Richard.Sandiford@arm.com>
> Subject: [aarch64] Update Neoverse N2 core definition
> 
> Hi,
> 
> As requested, I updated the Neoverse N2 entry to use the
> AARCH64_FL_FOR_ARCH9 feature set, removed duplicate entries, updated
> the
> ARCH_INDENT to 9A and moved it under the Armv9 cores.
> 

Ok, I should have said that the change is pre-approved.
Thanks,
Kyrill

> gcc/ChangeLog:
> 
>          * config/aarch64/aarch64-cores.def: Update Neoverse N2 core entry.
diff mbox series

Patch

diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def
index 9e6ca84bd4b277ccf2c1809c419703a23075f315..41d95354b6a483926b82a64ee6788eaf41814108 100644
--- a/gcc/config/aarch64/aarch64-cores.def
+++ b/gcc/config/aarch64/aarch64-cores.def
@@ -145,9 +145,6 @@  AARCH64_CORE("neoverse-512tvb", neoverse512tvb, cortexa57, 8_4A,  AARCH64_FL_FOR
 /* Qualcomm ('Q') cores. */
 AARCH64_CORE("saphira",     saphira,    saphira,    8_4A,  AARCH64_FL_FOR_ARCH8_4 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira,   0x51, 0xC01, -1)
 
-/* Armv8.5-A Architecture Processors.  */
-AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, 8_5A, AARCH64_FL_FOR_ARCH8_5 | AARCH64_FL_I8MM | AARCH64_FL_BF16 | AARCH64_FL_F16 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_BITPERM | AARCH64_FL_RNG | AARCH64_FL_MEMTAG, neoversen2, 0x41, 0xd49, -1)
-
 /* ARMv8-A big.LITTLE implementations.  */
 
 AARCH64_CORE("cortex-a57.cortex-a53",  cortexa57cortexa53, cortexa53, 8A,  AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03), -1)
@@ -172,6 +169,8 @@  AARCH64_CORE("cortex-a710",  cortexa710, cortexa57, 9A,  AARCH64_FL_FOR_ARCH9 |
 
 AARCH64_CORE("cortex-x2",  cortexx2, cortexa57, 9A,  AARCH64_FL_FOR_ARCH9 | AARCH64_FL_SVE2_BITPERM | AARCH64_FL_MEMTAG | AARCH64_FL_I8MM | AARCH64_FL_BF16, neoversen2, 0x41, 0xd48, -1)
 
+AARCH64_CORE("neoverse-n2", neoversen2, cortexa57, 9A, AARCH64_FL_FOR_ARCH9 | AARCH64_FL_I8MM | AARCH64_FL_BF16 | AARCH64_FL_SVE2_BITPERM | AARCH64_FL_RNG | AARCH64_FL_MEMTAG | AARCH64_FL_PROFILE, neoversen2, 0x41, 0xd49, -1)
+
 AARCH64_CORE("demeter", demeter, cortexa57, 9A, AARCH64_FL_FOR_ARCH9 | AARCH64_FL_I8MM | AARCH64_FL_BF16 | AARCH64_FL_SVE2_BITPERM | AARCH64_FL_RNG | AARCH64_FL_MEMTAG | AARCH64_FL_PROFILE, demeter, 0x41, 0xd4f, -1)
 
 #undef AARCH64_CORE