Message ID | 20220125161821.1951906-1-dinguyen@kernel.org |
---|---|
State | Not Applicable, archived |
Headers | show |
Series | [1/3] dt-bindings: usb: dwc2: add compatible "intel,socfpga-agilex-hsotg" | expand |
Context | Check | Description |
---|---|---|
robh/checkpatch | success | |
robh/dtbs-check | warning | build log |
robh/dt-meta-schema | success |
On 1/25/2022 8:18 PM, Dinh Nguyen wrote: > The DWC2 IP on the Agilex platform does not support clock-gating. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Acked-by: Minas Harutyunyan <Minas.Harutyunyan@synopsys.com> > --- > drivers/usb/dwc2/params.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c > index d300ae3d9274..1306f4ec788d 100644 > --- a/drivers/usb/dwc2/params.c > +++ b/drivers/usb/dwc2/params.c > @@ -82,6 +82,14 @@ static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg) > p->phy_utmi_width = 8; > } > > +static void dwc2_set_socfpga_agilex_params(struct dwc2_hsotg *hsotg) > +{ > + struct dwc2_core_params *p = &hsotg->params; > + > + p->power_down = DWC2_POWER_DOWN_PARAM_NONE; > + p->no_clock_gating = true; > +} > + > static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg) > { > struct dwc2_core_params *p = &hsotg->params; > @@ -239,6 +247,8 @@ const struct of_device_id dwc2_of_match_table[] = { > .data = dwc2_set_stm32mp15_fsotg_params }, > { .compatible = "st,stm32mp15-hsotg", > .data = dwc2_set_stm32mp15_hsotg_params }, > + { .compatible = "intel,socfpga-agilex-hsotg", > + .data = dwc2_set_socfpga_agilex_params }, > {}, > }; > MODULE_DEVICE_TABLE(of, dwc2_of_match_table);
On Tue, 25 Jan 2022 10:18:19 -0600, Dinh Nguyen wrote: > Add the compatible "intel,socfpga-agilex-hsotg" to the DWC2 > implementation, because the Agilex DWC2 implementation does not support > clock gating. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- > Documentation/devicetree/bindings/usb/dwc2.yaml | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org>
On Tue, Jan 25, 2022 at 10:18:21AM -0600, Dinh Nguyen wrote: > The DWC2 USB controller on the Agilex platform does not support clock > gating, so use the chip specific "intel,socfpga-agilex-hsotg" > compatible. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- > arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi > index 0dd2d2ee765a..f4270cf18996 100644 > --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi > @@ -502,7 +502,7 @@ uart1: serial@ffc02100 { > }; > > usb0: usb@ffb00000 { > - compatible = "snps,dwc2"; > + compatible = "intel,socfpga-agilex-hsotg", "snps,dwc2"; In the same patchset you sent a bindings change which is contradictory to this DTS change. This is wrong here and dtbs_check will complain.
On Tue, Jan 25, 2022 at 10:18:19AM -0600, Dinh Nguyen wrote: > Add the compatible "intel,socfpga-agilex-hsotg" to the DWC2 > implementation, because the Agilex DWC2 implementation does not support > clock gating. > > Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> > --- > Documentation/devicetree/bindings/usb/dwc2.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml > index f00867ebc147..481aaa09f3f2 100644 > --- a/Documentation/devicetree/bindings/usb/dwc2.yaml > +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml > @@ -53,6 +53,7 @@ properties: > - const: st,stm32mp15-hsotg > - const: snps,dwc2 > - const: samsung,s3c6400-hsotg > + - const: intel,socfpga-agilex-hsotg This is confusing and wrong. Now the intel,socfpga-agilex-hsotg is mentioned twice - with and without snps,dwc2. The DTS change in this patchset added usage with snps,dwc2. The commit msg says it's different, but is the difference incompatible? Please clarify the AgileX HSOTG - is it compatible with snps,dwc2 or not? Based on this the patch might need to be reverted (or changed). Best regards, Krzysztof
diff --git a/Documentation/devicetree/bindings/usb/dwc2.yaml b/Documentation/devicetree/bindings/usb/dwc2.yaml index f00867ebc147..481aaa09f3f2 100644 --- a/Documentation/devicetree/bindings/usb/dwc2.yaml +++ b/Documentation/devicetree/bindings/usb/dwc2.yaml @@ -53,6 +53,7 @@ properties: - const: st,stm32mp15-hsotg - const: snps,dwc2 - const: samsung,s3c6400-hsotg + - const: intel,socfpga-agilex-hsotg reg: maxItems: 1
Add the compatible "intel,socfpga-agilex-hsotg" to the DWC2 implementation, because the Agilex DWC2 implementation does not support clock gating. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> --- Documentation/devicetree/bindings/usb/dwc2.yaml | 1 + 1 file changed, 1 insertion(+)