Message ID | 20220124023125.414794-1-aford173@gmail.com |
---|---|
Headers | show |
Series | media: hantro: imx8mq/imx8mm: Let VPU decoders get controlled by vpu-blk-ctrl | expand |
Hi Adam, On Sun, Jan 23, 2022 at 08:31:23PM -0600, Adam Ford wrote: > The i.MX8MM has a Hantro G1 video decoder similar to the > imx8mq but lacks the post-processor present in the imx8mq. > Add support in the driver for it with the post-processing > removed. > > Signed-off-by: Adam Ford <aford173@gmail.com> > Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Thanks a lot, Ezequiel > diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c > index a670ddd29c4c..b281ac4fb79c 100644 > --- a/drivers/staging/media/hantro/hantro_drv.c > +++ b/drivers/staging/media/hantro/hantro_drv.c > @@ -615,6 +615,7 @@ static const struct of_device_id of_hantro_match[] = { > { .compatible = "rockchip,rk3399-vpu", .data = &rk3399_vpu_variant, }, > #endif > #ifdef CONFIG_VIDEO_HANTRO_IMX8M > + { .compatible = "nxp,imx8mm-vpu-g1", .data = &imx8mm_vpu_g1_variant, }, > { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, > { .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant }, > { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant }, > diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h > index f0bd2ffe290b..c00b46e06055 100644 > --- a/drivers/staging/media/hantro/hantro_hw.h > +++ b/drivers/staging/media/hantro/hantro_hw.h > @@ -299,6 +299,7 @@ enum hantro_enc_fmt { > ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3, > }; > > +extern const struct hantro_variant imx8mm_vpu_g1_variant; > extern const struct hantro_variant imx8mq_vpu_g1_variant; > extern const struct hantro_variant imx8mq_vpu_g2_variant; > extern const struct hantro_variant imx8mq_vpu_variant; > diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c > index 849ea7122d47..9802508bade2 100644 > --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c > +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c > @@ -327,3 +327,15 @@ const struct hantro_variant imx8mq_vpu_g2_variant = { > .clk_names = imx8mq_g2_clk_names, > .num_clocks = ARRAY_SIZE(imx8mq_g2_clk_names), > }; > + > +const struct hantro_variant imx8mm_vpu_g1_variant = { > + .dec_fmts = imx8m_vpu_dec_fmts, > + .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts), > + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | > + HANTRO_H264_DECODER, > + .codec_ops = imx8mq_vpu_g1_codec_ops, > + .irqs = imx8mq_irqs, > + .num_irqs = ARRAY_SIZE(imx8mq_irqs), > + .clk_names = imx8mq_g1_clk_names, > + .num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names), > +}; > -- > 2.32.0 >
On Sun, Jan 23, 2022 at 08:31:20PM -0600, Adam Ford wrote: > With the Hantro G1 and G2 now setup to run independently, update > the device tree to allow both to operate. This requires the > vpu-blk-ctrl node to be configured. Since vpu-blk-ctrl needs > certain clock enabled to handle the gating of the G1 and G2 > fuses, the clock-parents and clock-rates for the various VPU's > to be moved into the pgc_vpu because they cannot get re-parented > once enabled, and the pgc_vpu is the highest in the chain. > > Signed-off-by: Adam Ford <aford173@gmail.com> > Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Thanks, Ezequiel > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 2df2510d0118..549b2440f55d 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 { > pgc_vpu: power-domain@6 { > #power-domain-cells = <0>; > reg = <IMX8M_POWER_DOMAIN_VPU>; > - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, > + <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; > + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, > + <&clk IMX8MQ_CLK_VPU_G2>, > + <&clk IMX8MQ_CLK_VPU_BUS>, > + <&clk IMX8MQ_VPU_PLL_BYPASS>; > + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, > + <&clk IMX8MQ_VPU_PLL_OUT>, > + <&clk IMX8MQ_SYS1_PLL_800M>, > + <&clk IMX8MQ_VPU_PLL>; > + assigned-clock-rates = <600000000>, > + <600000000>, > + <800000000>, > + <0>; > }; > > pgc_disp: power-domain@7 { > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 { > status = "disabled"; > }; > > - vpu: video-codec@38300000 { > - compatible = "nxp,imx8mq-vpu"; > - reg = <0x38300000 0x10000>, > - <0x38310000 0x10000>, > - <0x38320000 0x10000>; > - reg-names = "g1", "g2", "ctrl"; > - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "g1", "g2"; > + vpu_g1: video-codec@38300000 { > + compatible = "nxp,imx8mq-vpu-g1"; > + reg = <0x38300000 0x10000>; > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; > + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; > + }; > + > + vpu_g2: video-codec@38310000 { > + compatible = "nxp,imx8mq-vpu-g2"; > + reg = <0x38310000 0x10000>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; > + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; > + }; > + > + vpu_blk_ctrl: blk-ctrl@38320000 { > + compatible = "fsl,imx8mq-vpu-blk-ctrl"; > + reg = <0x38320000 0x100>; > + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; > + power-domain-names = "bus", "g1", "g2"; > clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > - <&clk IMX8MQ_CLK_VPU_G2_ROOT>, > - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > - clock-names = "g1", "g2", "bus"; > - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, > - <&clk IMX8MQ_CLK_VPU_G2>, > - <&clk IMX8MQ_CLK_VPU_BUS>, > - <&clk IMX8MQ_VPU_PLL_BYPASS>; > - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, > - <&clk IMX8MQ_VPU_PLL_OUT>, > - <&clk IMX8MQ_SYS1_PLL_800M>, > - <&clk IMX8MQ_VPU_PLL>; > - assigned-clock-rates = <600000000>, <600000000>, > - <800000000>, <0>; > - power-domains = <&pgc_vpu>; > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; > + clock-names = "g1", "g2"; > + #power-domain-cells = <1>; > }; > > pcie0: pcie@33800000 { > -- > 2.32.0 >
Hi Adam, On Sun, Jan 23, 2022 at 08:31:19PM -0600, Adam Ford wrote: > The VPU in the i.MX8MQ is really the combination of Hantro G1 and > Hantro G2. With the updated vpu-blk-ctrl, the power domains system > can enable and disable them separately as well as pull them out of > reset. This simplifies the code and lets them run independently > while still retaining backwards compatibility with older device > trees for those using G1. > > Signed-off-by: Adam Ford <aford173@gmail.com> > > diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c > index 6a51f39dde56..a670ddd29c4c 100644 > --- a/drivers/staging/media/hantro/hantro_drv.c > +++ b/drivers/staging/media/hantro/hantro_drv.c > @@ -616,6 +616,7 @@ static const struct of_device_id of_hantro_match[] = { > #endif > #ifdef CONFIG_VIDEO_HANTRO_IMX8M > { .compatible = "nxp,imx8mq-vpu", .data = &imx8mq_vpu_variant, }, Since you might need to resend the series anyway due to the issue with arch/arm64/boot/dts/freescale/imx8mq-tqma8mq.dtsi, could you add a small warning for the deprecated compatible string? This will be a useful hint for kernel developers and system integrators about the devicetree changes. Something along these lines, maybe? match = of_match_node(of_hantro_match, pdev->dev.of_node); vpu->variant = match->data; /* * Support for nxp,imx8mq-vpu is kept for backwards compatibility * but it's deprecated. Please update your DTS file to use * nxp,imx8mq-vpu-g1 or nxp,imx8mq-vpu-g2 instead. */ if (of_device_is_compatible(pdev->dev.of_node, "nxp,imx8mq-vpu")) dev_warn(&pdev->dev, "%s compatible is deprecated\n", match->compatible); In any case, the patch looks good: Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Thanks, Ezequiel > + { .compatible = "nxp,imx8mq-vpu-g1", .data = &imx8mq_vpu_g1_variant }, > { .compatible = "nxp,imx8mq-vpu-g2", .data = &imx8mq_vpu_g2_variant }, > #endif > #ifdef CONFIG_VIDEO_HANTRO_SAMA5D4 > diff --git a/drivers/staging/media/hantro/hantro_hw.h b/drivers/staging/media/hantro/hantro_hw.h > index 4a19ae8940b9..f0bd2ffe290b 100644 > --- a/drivers/staging/media/hantro/hantro_hw.h > +++ b/drivers/staging/media/hantro/hantro_hw.h > @@ -299,6 +299,7 @@ enum hantro_enc_fmt { > ROCKCHIP_VPU_ENC_FMT_UYVY422 = 3, > }; > > +extern const struct hantro_variant imx8mq_vpu_g1_variant; > extern const struct hantro_variant imx8mq_vpu_g2_variant; > extern const struct hantro_variant imx8mq_vpu_variant; > extern const struct hantro_variant px30_vpu_variant; > diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c > index f5991b8e553a..849ea7122d47 100644 > --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c > +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c > @@ -205,13 +205,6 @@ static void imx8m_vpu_g1_reset(struct hantro_ctx *ctx) > imx8m_soft_reset(vpu, RESET_G1); > } > > -static void imx8m_vpu_g2_reset(struct hantro_ctx *ctx) > -{ > - struct hantro_dev *vpu = ctx->dev; > - > - imx8m_soft_reset(vpu, RESET_G2); > -} > - > /* > * Supported codec ops. > */ > @@ -237,17 +230,33 @@ static const struct hantro_codec_ops imx8mq_vpu_codec_ops[] = { > }, > }; > > +static const struct hantro_codec_ops imx8mq_vpu_g1_codec_ops[] = { > + [HANTRO_MODE_MPEG2_DEC] = { > + .run = hantro_g1_mpeg2_dec_run, > + .init = hantro_mpeg2_dec_init, > + .exit = hantro_mpeg2_dec_exit, > + }, > + [HANTRO_MODE_VP8_DEC] = { > + .run = hantro_g1_vp8_dec_run, > + .init = hantro_vp8_dec_init, > + .exit = hantro_vp8_dec_exit, > + }, > + [HANTRO_MODE_H264_DEC] = { > + .run = hantro_g1_h264_dec_run, > + .init = hantro_h264_dec_init, > + .exit = hantro_h264_dec_exit, > + }, > +}; > + > static const struct hantro_codec_ops imx8mq_vpu_g2_codec_ops[] = { > [HANTRO_MODE_HEVC_DEC] = { > .run = hantro_g2_hevc_dec_run, > - .reset = imx8m_vpu_g2_reset, > .init = hantro_hevc_dec_init, > .exit = hantro_hevc_dec_exit, > }, > [HANTRO_MODE_VP9_DEC] = { > .run = hantro_g2_vp9_dec_run, > .done = hantro_g2_vp9_dec_done, > - .reset = imx8m_vpu_g2_reset, > .init = hantro_vp9_dec_init, > .exit = hantro_vp9_dec_exit, > }, > @@ -267,6 +276,8 @@ static const struct hantro_irq imx8mq_g2_irqs[] = { > > static const char * const imx8mq_clk_names[] = { "g1", "g2", "bus" }; > static const char * const imx8mq_reg_names[] = { "g1", "g2", "ctrl" }; > +static const char * const imx8mq_g1_clk_names[] = { "g1" }; > +static const char * const imx8mq_g2_clk_names[] = { "g2" }; > > const struct hantro_variant imx8mq_vpu_variant = { > .dec_fmts = imx8m_vpu_dec_fmts, > @@ -287,6 +298,21 @@ const struct hantro_variant imx8mq_vpu_variant = { > .num_regs = ARRAY_SIZE(imx8mq_reg_names) > }; > > +const struct hantro_variant imx8mq_vpu_g1_variant = { > + .dec_fmts = imx8m_vpu_dec_fmts, > + .num_dec_fmts = ARRAY_SIZE(imx8m_vpu_dec_fmts), > + .postproc_fmts = imx8m_vpu_postproc_fmts, > + .num_postproc_fmts = ARRAY_SIZE(imx8m_vpu_postproc_fmts), > + .postproc_ops = &hantro_g1_postproc_ops, > + .codec = HANTRO_MPEG2_DECODER | HANTRO_VP8_DECODER | > + HANTRO_H264_DECODER, > + .codec_ops = imx8mq_vpu_g1_codec_ops, > + .irqs = imx8mq_irqs, > + .num_irqs = ARRAY_SIZE(imx8mq_irqs), > + .clk_names = imx8mq_g1_clk_names, > + .num_clocks = ARRAY_SIZE(imx8mq_g1_clk_names), > +}; > + > const struct hantro_variant imx8mq_vpu_g2_variant = { > .dec_offset = 0x0, > .dec_fmts = imx8m_vpu_g2_dec_fmts, > @@ -296,10 +322,8 @@ const struct hantro_variant imx8mq_vpu_g2_variant = { > .postproc_ops = &hantro_g2_postproc_ops, > .codec = HANTRO_HEVC_DECODER | HANTRO_VP9_DECODER, > .codec_ops = imx8mq_vpu_g2_codec_ops, > - .init = imx8mq_vpu_hw_init, > - .runtime_resume = imx8mq_runtime_resume, > .irqs = imx8mq_g2_irqs, > .num_irqs = ARRAY_SIZE(imx8mq_g2_irqs), > - .clk_names = imx8mq_clk_names, > - .num_clocks = ARRAY_SIZE(imx8mq_clk_names), > + .clk_names = imx8mq_g2_clk_names, > + .num_clocks = ARRAY_SIZE(imx8mq_g2_clk_names), > }; > -- > 2.32.0 >
Hi Adam, On Sun, Jan 23, 2022 at 08:31:24PM -0600, Adam Ford wrote: > There are two decoders on the i.MX8M Mini controlled by the > vpu-blk-ctrl. The G1 supports H264 and VP8 while the > G2 support HEVC and VP9. > > Signed-off-by: Adam Ford <aford173@gmail.com> > Looks good. Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar> Thanks, Ezequiel > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > index 0c7a72c51a31..98aec4421713 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi > @@ -1272,6 +1272,22 @@ gpu_2d: gpu@38008000 { > power-domains = <&pgc_gpu>; > }; > > + vpu_g1: video-codec@38300000 { > + compatible = "nxp,imx8mm-vpu-g1"; > + reg = <0x38300000 0x10000>; > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MM_CLK_VPU_G1_ROOT>; > + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>; > + }; > + > + vpu_g2: video-codec@38310000 { > + compatible = "nxp,imx8mq-vpu-g2"; > + reg = <0x38310000 0x10000>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MM_CLK_VPU_G2_ROOT>; > + power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>; > + }; > + > vpu_blk_ctrl: blk-ctrl@38330000 { > compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon"; > reg = <0x38330000 0x100>; > @@ -1282,6 +1298,12 @@ vpu_blk_ctrl: blk-ctrl@38330000 { > <&clk IMX8MM_CLK_VPU_G2_ROOT>, > <&clk IMX8MM_CLK_VPU_H1_ROOT>; > clock-names = "g1", "g2", "h1"; > + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, > + <&clk IMX8MM_CLK_VPU_G2>; > + assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>, > + <&clk IMX8MM_VPU_PLL_OUT>; > + assigned-clock-rates = <600000000>, > + <600000000>; > #power-domain-cells = <1>; > }; > > -- > 2.32.0 >