diff mbox series

[arm] MVE: Relax addressing modes for full loads and stores

Message ID 52549bc7-2784-c721-0420-67ad4d40a5ca@arm.com
State New
Headers show
Series [arm] MVE: Relax addressing modes for full loads and stores | expand

Commit Message

Andre Vieira (lists) Jan. 14, 2022, 5:03 p.m. UTC 
Hi Christophe,

This patch relaxes the addressing modes for the mve full load and stores 
(by full loads and stores I mean non-widening or narrowing loads and 
stores resp). The code before was requiring a LO_REGNUM for these, where 
this is only a requirement if the load is widening or the store narrowing.

So with this your patch should not be necessary.

Regression tested on arm-none-eabi-gcc.  Can you please confirm this 
fixes the issue you were seeing too?

gcc/ChangeLog:

         * config/arm/arm.h (MVE_STN_LDW_MODE): New MACRO.
         * config/arm/arm.c (mve_vector_mem_operand): Relax constraint on
         base register for non widening loads or narrowing stores.


Kind Regards,
Andre Vieira

Comments

Christophe Lyon Jan. 17, 2022, 7:48 a.m. UTC | #1 
Hi André,

On Fri, Jan 14, 2022 at 6:03 PM Andre Vieira (lists) via Gcc-patches <
gcc-patches@gcc.gnu.org> wrote:

> Hi Christophe,
>
> This patch relaxes the addressing modes for the mve full load and stores
> (by full loads and stores I mean non-widening or narrowing loads and
> stores resp). The code before was requiring a LO_REGNUM for these, where
> this is only a requirement if the load is widening or the store narrowing.
>
> So with this your patch should not be necessary.
>
> Regression tested on arm-none-eabi-gcc.  Can you please confirm this
> fixes the issue you were seeing too?
>

Yes, I confirm this fixes the problem I was fixing with my patch #15 in my
MVE/VCMP/VCOND series.
I'll drop it.

Thanks!

Christophe


>
> gcc/ChangeLog:
>
>          * config/arm/arm.h (MVE_STN_LDW_MODE): New MACRO.
>          * config/arm/arm.c (mve_vector_mem_operand): Relax constraint on
>          base register for non widening loads or narrowing stores.
>
>
> Kind Regards,
> Andre Vieira
Andre Vieira (lists) March 7, 2022, 2:16 p.m. UTC | #2 
On 17/01/2022 07:48, Christophe Lyon wrote:
> Hi André,
>
> On Fri, Jan 14, 2022 at 6:03 PM Andre Vieira (lists) via Gcc-patches 
> <gcc-patches@gcc.gnu.org> wrote:
>
>     Hi Christophe,
>
>     This patch relaxes the addressing modes for the mve full load and
>     stores
>     (by full loads and stores I mean non-widening or narrowing loads and
>     stores resp). The code before was requiring a LO_REGNUM for these,
>     where
>     this is only a requirement if the load is widening or the store
>     narrowing.
>
>     So with this your patch should not be necessary.
>
>     Regression tested on arm-none-eabi-gcc.  Can you please confirm this
>     fixes the issue you were seeing too?
>
>
> Yes, I confirm this fixes the problem I was fixing with my patch #15 
> in my MVE/VCMP/VCOND series.
> I'll drop it.
>
> Thanks!
>
> Christophe
>
>
>     gcc/ChangeLog:
>
>              * config/arm/arm.h (MVE_STN_LDW_MODE): New MACRO.
>              * config/arm/arm.c (mve_vector_mem_operand): Relax
>     constraint on
>              base register for non widening loads or narrowing stores.
>
>
>     Kind Regards,
>     Andre Vieira
>

Ping, I noticed this also fixes PR 104790.

Kind regards,
Andre
Kyrylo Tkachov March 7, 2022, 4:14 p.m. UTC | #3 
Ok, please include PR 104790 in the ChangeLog.
Thanks,
Kyrill

From: Andre Vieira (lists) <andre.simoesdiasvieira@arm.com>
Sent: Monday, March 7, 2022 2:17 PM
To: Kyrylo Tkachov <Kyrylo.Tkachov@arm.com>
Cc: GCC Patches <gcc-patches@gcc.gnu.org>
Subject: Re: [arm] MVE: Relax addressing modes for full loads and stores

On 17/01/2022 07:48, Christophe Lyon wrote:
Hi André,

On Fri, Jan 14, 2022 at 6:03 PM Andre Vieira (lists) via Gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>> wrote:
Hi Christophe,

This patch relaxes the addressing modes for the mve full load and stores
(by full loads and stores I mean non-widening or narrowing loads and
stores resp). The code before was requiring a LO_REGNUM for these, where
this is only a requirement if the load is widening or the store narrowing.

So with this your patch should not be necessary.

Regression tested on arm-none-eabi-gcc.  Can you please confirm this
fixes the issue you were seeing too?

Yes, I confirm this fixes the problem I was fixing with my patch #15 in my MVE/VCMP/VCOND series.
I'll drop it.

Thanks!

Christophe


gcc/ChangeLog:

         * config/arm/arm.h (MVE_STN_LDW_MODE): New MACRO.
         * config/arm/arm.c (mve_vector_mem_operand): Relax constraint on
         base register for non widening loads or narrowing stores.


Kind Regards,
Andre Vieira



Ping, I noticed this also fixes PR 104790.

Kind regards,
Andre
diff mbox series

Patch

diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index dacce2b7f086eeffb0cd36b26f102f77130a92fa..f39786d0f9e19e81841a45f6d7e92e408272fe23 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -1099,6 +1099,10 @@  extern const int arm_arch_cde_coproc_bits[];
   ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \
    || (MODE) == V16QImode)
 
+/* Modes used in MVE's narrowing stores or widening loads.  */
+#define MVE_STN_LDW_MODE(MODE) \
+  ((MODE) == V4QImode || (MODE) == V8QImode || (MODE) == V4HImode)
+
 #define VALID_MVE_SF_MODE(MODE) \
   ((MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DFmode)
 
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c
index bb75921f32df6185711d5304c044ce67a2d5671e..f5e09cb00b5478546d29c05cc885aeaa89501d39 100644
--- a/gcc/config/arm/arm.c
+++ b/gcc/config/arm/arm.c
@@ -13438,27 +13438,28 @@  mve_vector_mem_operand (machine_mode mode, rtx op, bool strict)
 	  case E_V16QImode:
 	  case E_V8QImode:
 	  case E_V4QImode:
-	    if (abs (val) <= 127)
-	      return (reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM)
-		|| reg_no >= FIRST_PSEUDO_REGISTER;
-	    return FALSE;
+	    if (abs (val) > 127)
+	      return FALSE;
+	    break;
 	  case E_V8HImode:
 	  case E_V8HFmode:
 	  case E_V4HImode:
 	  case E_V4HFmode:
-	    if (val % 2 == 0 && abs (val) <= 254)
-	      return reg_no <= LAST_LO_REGNUM
-		|| reg_no >= FIRST_PSEUDO_REGISTER;
-	    return FALSE;
+	    if (val % 2 != 0 || abs (val) > 254)
+	      return FALSE;
+	    break;
 	  case E_V4SImode:
 	  case E_V4SFmode:
-	    if (val % 4 == 0 && abs (val) <= 508)
-	      return (reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM)
-		|| reg_no >= FIRST_PSEUDO_REGISTER;
-	    return FALSE;
+	    if (val % 4 != 0 || abs (val) > 508)
+	      return FALSE;
+	    break;
 	  default:
 	    return FALSE;
 	}
+      return reg_no >= FIRST_PSEUDO_REGISTER
+	|| (MVE_STN_LDW_MODE (mode)
+	    ? reg_no <= LAST_LO_REGNUM
+	    : (reg_no < LAST_ARM_REGNUM && reg_no != SP_REGNUM));
     }
   return FALSE;
 }