| Message ID | 1638432158-4119-6-git-send-email-hongxing.zhu@nxp.com |
|---|---|
| State | New |
| Headers | show |
| Series | Add the imx8m pcie phy driver and imx8mm pcie support | expand |
On 02-12-21, 16:02, Richard Zhu wrote:
> Add the standalone i.MX8 PCIe PHY driver.
Applied, thanks
Hi Richard, I've run into an issue that appears to indicate a functional difference between the existing integrated pci-imx6.c implementation and this new implementation with the separate phy driver. I'm working with a SOM and baseboard from Phytec that is based on the IMX8MM. The board does not have an external PCIe clock and has a ethernet controller hanging off the PCIe bus. When booting from a 5.4 NXP-based kernel from Phytec the ethernet controller is probed and functions as expected. A co-worker backported a slightly earlier version of this patchset to 5.10.[1] With our kernel both the controller driver and new PHY driver are probed, but a timeout occurs in dw_pcie_wait_for_link() which indicates that the "Phy link never came up". After reproducing this issue I configured pcie_phy with IMX8_PCIE_REFCLK_PAD_OUTPUT. With that configured, phy register CMN_REG062/0x188 matches the 5.4 NXP/Phytec kernel. I then compared the controller and PHY registers between the two kernels and noticed that CMN_REG063/0x18c is set to AUX_IN/0x0 in the 5.4 NXP/Phytec kernel, but the new PHY driver writes I_PLL_REFCLK_FROM_SYSPLL/0xc0 to that register. If I modify the phy driver to not write I_PLL_REFCLK_FROM_SYSPLL/0xc0 then the system behaves as expected. Best, Philip [1]: I plan on rebasing our branch with the latest patches that have been applied upstream. Note that I did not see any difference in the following code with what we have applied. On 12/2/21 09:02, Richard Zhu wrote: > +#define IMX8MM_PCIE_PHY_CMN_REG061 0x184 > +#define ANA_PLL_CLK_OUT_TO_EXT_IO_EN BIT(0) > +#define IMX8MM_PCIE_PHY_CMN_REG062 0x188 > +#define ANA_PLL_CLK_OUT_TO_EXT_IO_SEL BIT(3) > +#define IMX8MM_PCIE_PHY_CMN_REG063 0x18C > +#define AUX_PLL_REFCLK_SEL_SYS_PLL GENMASK(7, 6) > +#define IMX8MM_PCIE_PHY_CMN_REG064 0x190 > +#define ANA_AUX_RX_TX_SEL_TX BIT(7) > +#define ANA_AUX_RX_TERM_GND_EN BIT(3) > +#define ANA_AUX_TX_TERM BIT(2) > +#define IMX8MM_PCIE_PHY_CMN_REG065 0x194 > +#define ANA_AUX_RX_TERM (BIT(7) | BIT(4)) > +#define ANA_AUX_TX_LVL GENMASK(3, 0) ... > + if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT) { > + /* Configure the pad as input */ > + val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); > + writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN, > + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); > + } else if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) { > + /* Configure the PHY to output the refclock via pad */ > + writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN, > + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); > + writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL, > + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062); > + writel(AUX_PLL_REFCLK_SEL_SYS_PLL, > + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063); If I comment out this writel() then the register defaults to 0x0/AUX_IN and then the system behaves as expected. > + val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM; > + writel(val | ANA_AUX_RX_TERM_GND_EN, > + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064); > + writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL, > + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065); > + }
> -----Original Message----- > From: Philip Molloy <philip@linutronix.de> > Sent: Wednesday, December 29, 2021 8:40 PM > To: Hongxing Zhu <hongxing.zhu@nxp.com> > Cc: l.stach@pengutronix.de; bhelgaas@google.com; > lorenzo.pieralisi@arm.com; tharvey@gateworks.com; Marcel Ziswiler > <marcel.ziswiler@toradex.com>; kishon@ti.com; vkoul@kernel.org; > robh@kernel.org; galak@kernel.crashing.org; shawnguo@kernel.org; > linux-phy@lists.infradead.org; devicetree@vger.kernel.org; > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx > <linux-imx@nxp.com> > Subject: Re: [PATCH v7 5/8] phy: freescale: pcie: Initialize the imx8 pcie > standalone phy driver > > Hi Richard, > > I've run into an issue that appears to indicate a functional difference > between the existing integrated pci-imx6.c implementation and this new > implementation with the separate phy driver. > > I'm working with a SOM and baseboard from Phytec that is based on the > IMX8MM. The board does not have an external PCIe clock and has a > ethernet controller hanging off the PCIe bus. > > When booting from a 5.4 NXP-based kernel from Phytec the ethernet > controller is probed and functions as expected. > > A co-worker backported a slightly earlier version of this patchset to > 5.10.[1] With our kernel both the controller driver and new PHY driver are > probed, but a timeout occurs in dw_pcie_wait_for_link() which indicates > that the "Phy link never came up". > > After reproducing this issue I configured pcie_phy with > IMX8_PCIE_REFCLK_PAD_OUTPUT. With that configured, phy register > CMN_REG062/0x188 matches the 5.4 NXP/Phytec kernel. I then > compared the controller and PHY registers between the two kernels and > noticed that CMN_REG063/0x18c is set to AUX_IN/0x0 in the 5.4 > NXP/Phytec kernel, but the new PHY driver writes > I_PLL_REFCLK_FROM_SYSPLL/0xc0 to that register. > > If I modify the phy driver to not write I_PLL_REFCLK_FROM_SYSPLL/0xc0 > then the system behaves as expected. [Richard Zhu] Hi Philip: The address 0x018C is a register to control the output mode of Refclk IO. When internal syspll is used as PHY REF clock. Regarding my understand, this register should select the syspll, and route it out of SOC from CLK N/P pads. Then the remote EP device can use the clock from CLK N/P pads. If the bit7-6 is set to 2b'00, there wouldn't clock output from CLK N/P pads. What's the hardware design of the CLK N/P pads in your project? Can you monitor the situation of the CLK N/P if it is possible? Best Regards Richard Zhu > > Best, > Philip > > [1]: I plan on rebasing our branch with the latest patches that have been > applied upstream. Note that I did not see any difference in the following > code with what we have applied. > > On 12/2/21 09:02, Richard Zhu wrote: > > +#define IMX8MM_PCIE_PHY_CMN_REG061 0x184 > > +#define ANA_PLL_CLK_OUT_TO_EXT_IO_EN BIT(0) > > +#define IMX8MM_PCIE_PHY_CMN_REG062 0x188 > > +#define ANA_PLL_CLK_OUT_TO_EXT_IO_SEL BIT(3) > > +#define IMX8MM_PCIE_PHY_CMN_REG063 0x18C > > +#define AUX_PLL_REFCLK_SEL_SYS_PLL GENMASK(7, 6) > > +#define IMX8MM_PCIE_PHY_CMN_REG064 0x190 > > +#define ANA_AUX_RX_TX_SEL_TX BIT(7) > > +#define ANA_AUX_RX_TERM_GND_EN BIT(3) > > +#define ANA_AUX_TX_TERM BIT(2) > > +#define IMX8MM_PCIE_PHY_CMN_REG065 0x194 > > +#define ANA_AUX_RX_TERM (BIT(7) | BIT(4)) > > +#define ANA_AUX_TX_LVL GENMASK(3, 0) > ... > > + if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT) { > > + /* Configure the pad as input */ > > + val = readl(imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG061); > > + writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG061); > > + } else if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) { > > + /* Configure the PHY to output the refclock via pad */ > > + writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG061); > > + writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG062); > > + writel(AUX_PLL_REFCLK_SEL_SYS_PLL, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG063); > > If I comment out this writel() then the register defaults to 0x0/AUX_IN > and then the system behaves as expected. > > > + val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM; > > + writel(val | ANA_AUX_RX_TERM_GND_EN, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG064); > > + writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL, > > + imx8_phy->base + > IMX8MM_PCIE_PHY_CMN_REG065); > > + }
On Thu, 2021-12-30 at 04:58 +0000, Hongxing Zhu wrote: > > -----Original Message----- > > From: Philip Molloy <philip@linutronix.de> > > Sent: Wednesday, December 29, 2021 8:40 PM > > To: Hongxing Zhu <hongxing.zhu@nxp.com> > > Cc: l.stach@pengutronix.de; bhelgaas@google.com; > > lorenzo.pieralisi@arm.com; tharvey@gateworks.com; Marcel Ziswiler > > <marcel.ziswiler@toradex.com>; kishon@ti.com; vkoul@kernel.org; > > robh@kernel.org; galak@kernel.crashing.org; shawnguo@kernel.org; > > linux-phy@lists.infradead.org; devicetree@vger.kernel.org; > > linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > > linux-kernel@vger.kernel.org; kernel@pengutronix.de; dl-linux-imx > > <linux-imx@nxp.com> > > Subject: Re: [PATCH v7 5/8] phy: freescale: pcie: Initialize the imx8 pcie > > standalone phy driver > > > > Hi Richard, > > > > I've run into an issue that appears to indicate a functional difference > > between the existing integrated pci-imx6.c implementation and this new > > implementation with the separate phy driver. > > > > I'm working with a SOM and baseboard from Phytec that is based on the > > IMX8MM. The board does not have an external PCIe clock and has a > > ethernet controller hanging off the PCIe bus. > > > > When booting from a 5.4 NXP-based kernel from Phytec the ethernet > > controller is probed and functions as expected. > > > > A co-worker backported a slightly earlier version of this patchset to > > 5.10.[1] With our kernel both the controller driver and new PHY driver are > > probed, but a timeout occurs in dw_pcie_wait_for_link() which indicates > > that the "Phy link never came up". > > > > After reproducing this issue I configured pcie_phy with > > IMX8_PCIE_REFCLK_PAD_OUTPUT. With that configured, phy register > > CMN_REG062/0x188 matches the 5.4 NXP/Phytec kernel. I then > > compared the controller and PHY registers between the two kernels and > > noticed that CMN_REG063/0x18c is set to AUX_IN/0x0 in the 5.4 > > NXP/Phytec kernel, but the new PHY driver writes > > I_PLL_REFCLK_FROM_SYSPLL/0xc0 to that register. > > > > If I modify the phy driver to not write I_PLL_REFCLK_FROM_SYSPLL/0xc0 > > then the system behaves as expected. > [Richard Zhu] > Hi Philip: > The address 0x018C is a register to control the output mode of Refclk IO. > When internal syspll is used as PHY REF clock. > Regarding my understand, this register should select the syspll, and route > it out of SOC from CLK N/P pads. > Then the remote EP device can use the clock from CLK N/P pads. > > If the bit7-6 is set to 2b'00, there wouldn't clock output from CLK N/P pads. > What's the hardware design of the CLK N/P pads in your project? > Can you monitor the situation of the CLK N/P if it is possible? I can confirm that for me similar hardware which also "does not have an external PCIe clock" works just fine with the following device tree sniped: &pcie0 { assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_CTRL>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, <&clk IMX8MM_SYS_PLL2_250M>; assigned-clock-rates = <10000000>, <250000000>; clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk IMX8MM_CLK_PCIE1_AUX>, <&clk IMX8MM_CLK_PCIE1_PHY>; clock-names = "pcie", "pcie_aux", "pcie_bus"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie0>; /* PCIE_1_RESET# (SODIMM 244) */ reset-gpio = <&gpio3 19 GPIO_ACTIVE_LOW>; status = "okay"; }; &pcie_phy { clocks = <&clk IMX8MM_CLK_PCIE1_PHY>; fsl,clkreq-unsupported; fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; fsl,tx-deemph-gen1 = <0x2d>; fsl,tx-deemph-gen2 = <0xf>; status = "okay"; }; During boot that looks as follows: [ 1.858312] imx6q-pcie 33800000.pcie: host bridge /soc@0/pcie@33800000 ranges: [ 1.865630] imx6q-pcie 33800000.pcie: IO 0x001ff80000..0x001ff8ffff -> 0x0000000000 [ 1.877833] imx6q-pcie 33800000.pcie: MEM 0x0018000000..0x001fefffff -> 0x0018000000 [ 1.992010] imx6q-pcie 33800000.pcie: iATU unroll: enabled [ 1.997523] imx6q-pcie 33800000.pcie: Detected iATU regions: 4 outbound, 4 inbound [ 2.103140] imx6q-pcie 33800000.pcie: Link up [ 2.107527] imx6q-pcie 33800000.pcie: Link up [ 2.111895] imx6q-pcie 33800000.pcie: Link up, Gen1 [ 2.116786] imx6q-pcie 33800000.pcie: Link up [ 2.121298] imx6q-pcie 33800000.pcie: PCI host bridge to bus 0000:00 [ 2.127671] pci_bus 0000:00: root bus resource [bus 00-ff] [ 2.133171] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] [ 2.139363] pci_bus 0000:00: root bus resource [mem 0x18000000-0x1fefffff] [ 2.146282] pci 0000:00:00.0: [16c3:abcd] type 01 class 0x060400 [ 2.152322] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x000fffff] [ 2.158612] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref] [ 2.165373] pci 0000:00:00.0: supports D1 [ 2.169395] pci 0000:00:00.0: PME# supported from D0 D1 D3hot D3cold [ 2.178101] pci 0000:01:00.0: [10ec:8168] type 00 class 0x020000 [ 2.184196] pci 0000:01:00.0: reg 0x10: [io 0x0000-0x00ff] [ 2.189864] pci 0000:01:00.0: reg 0x18: [mem 0x00000000-0x00000fff 64bit pref] [ 2.197152] pci 0000:01:00.0: reg 0x20: [mem 0x00000000-0x00003fff 64bit pref] [ 2.204777] pci 0000:01:00.0: supports D1 D2 [ 2.209059] pci 0000:01:00.0: PME# supported from D0 D1 D2 D3hot D3cold [ 2.229114] pci 0000:00:00.0: BAR 0: assigned [mem 0x18000000-0x180fffff] [ 2.235934] pci 0000:00:00.0: BAR 15: assigned [mem 0x18100000-0x181fffff pref] [ 2.243260] pci 0000:00:00.0: BAR 6: assigned [mem 0x18200000-0x1820ffff pref] [ 2.250501] pci 0000:00:00.0: BAR 13: assigned [io 0x1000-0x1fff] [ 2.256734] pci 0000:01:00.0: BAR 4: assigned [mem 0x18100000-0x18103fff 64bit pref] [ 2.264534] pci 0000:01:00.0: BAR 2: assigned [mem 0x18104000-0x18104fff 64bit pref] [ 2.272338] pci 0000:01:00.0: BAR 0: assigned [io 0x1000-0x10ff] [ 2.278460] pci 0000:00:00.0: PCI bridge to [bus 01-ff] [ 2.283698] pci 0000:00:00.0: bridge window [io 0x1000-0x1fff] [ 2.289808] pci 0000:00:00.0: bridge window [mem 0x18100000-0x181fffff pref] [ 2.297444] pcieport 0000:00:00.0: PME: Signaling with IRQ 225 And my mini-PCIe Ethernet card gets detected and is fully functional: [ 4.433899] r8169 0000:01:00.0: enabling device (0000 -> 0003) [ 4.466731] libphy: r8169: probed [ 4.476288] r8169 0000:01:00.0 eth1: RTL8168e/8111e, 00:e0:4c:80:f4:0d, XID 2c2, IRQ 229 [ 4.484485] r8169 0000:01:00.0 eth1: jumbo features [frames: 9194 bytes, tx checksumming: ko] [ 5.023616] r8169 0000:01:00.0 enp1s0: renamed from eth1 [ 6.713601] r8169 0000:01:00.0: Direct firmware load for rtl_nic/rtl8168e-2.fw failed with error -2 [ 6.722786] r8169 0000:01:00.0: Unable to load firmware rtl_nic/rtl8168e-2.fw (-2) [ 6.731391] RTL8211DN Gigabit Ethernet r8169-0-100:00: attached PHY driver (mii_bus:phy_addr=r8169-0-100:00, irq=MAC) [ 6.808798] r8169 0000:01:00.0 enp1s0: Link is Down root@verdin-imx8mm-06760554:~# lspci 00:00.0 PCI bridge: Synopsys, Inc. DWC_usb3 / PCIe bridge (rev 01) 01:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 06) Cheers Marcel > Best Regards > Richard Zhu > > > > > Best, > > Philip > > > > [1]: I plan on rebasing our branch with the latest patches that have been > > applied upstream. Note that I did not see any difference in the following > > code with what we have applied. > > > > On 12/2/21 09:02, Richard Zhu wrote: > > > +#define IMX8MM_PCIE_PHY_CMN_REG061 0x184 > > > +#define ANA_PLL_CLK_OUT_TO_EXT_IO_EN BIT(0) > > > +#define IMX8MM_PCIE_PHY_CMN_REG062 0x188 > > > +#define ANA_PLL_CLK_OUT_TO_EXT_IO_SEL BIT(3) > > > +#define IMX8MM_PCIE_PHY_CMN_REG063 0x18C > > > +#define AUX_PLL_REFCLK_SEL_SYS_PLL GENMASK(7, 6) > > > +#define IMX8MM_PCIE_PHY_CMN_REG064 0x190 > > > +#define ANA_AUX_RX_TX_SEL_TX BIT(7) > > > +#define ANA_AUX_RX_TERM_GND_EN BIT(3) > > > +#define ANA_AUX_TX_TERM BIT(2) > > > +#define IMX8MM_PCIE_PHY_CMN_REG065 0x194 > > > +#define ANA_AUX_RX_TERM (BIT(7) | BIT(4)) > > > +#define ANA_AUX_TX_LVL GENMASK(3, 0) > > ... > > > + if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT) { > > > + /* Configure the pad as input */ > > > + val = readl(imx8_phy->base + > > IMX8MM_PCIE_PHY_CMN_REG061); > > > + writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN, > > > + imx8_phy->base + > > IMX8MM_PCIE_PHY_CMN_REG061); > > > + } else if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) { > > > + /* Configure the PHY to output the refclock via pad */ > > > + writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN, > > > + imx8_phy->base + > > IMX8MM_PCIE_PHY_CMN_REG061); > > > + writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL, > > > + imx8_phy->base + > > IMX8MM_PCIE_PHY_CMN_REG062); > > > + writel(AUX_PLL_REFCLK_SEL_SYS_PLL, > > > + imx8_phy->base + > > IMX8MM_PCIE_PHY_CMN_REG063); > > > > If I comment out this writel() then the register defaults to 0x0/AUX_IN > > and then the system behaves as expected. > > > > > + val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM; > > > + writel(val | ANA_AUX_RX_TERM_GND_EN, > > > + imx8_phy->base + > > IMX8MM_PCIE_PHY_CMN_REG064); > > > + writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL, > > > + imx8_phy->base + > > IMX8MM_PCIE_PHY_CMN_REG065); > > > + }
diff --git a/drivers/phy/freescale/Kconfig b/drivers/phy/freescale/Kconfig index 320630ffe3cd..c3669c28ea9f 100644 --- a/drivers/phy/freescale/Kconfig +++ b/drivers/phy/freescale/Kconfig @@ -14,3 +14,11 @@ config PHY_MIXEL_MIPI_DPHY help Enable this to add support for the Mixel DSI PHY as found on NXP's i.MX8 family of SOCs. + +config PHY_FSL_IMX8M_PCIE + tristate "Freescale i.MX8M PCIE PHY" + depends on OF && HAS_IOMEM + select GENERIC_PHY + help + Enable this to add support for the PCIE PHY as found on + i.MX8M family of SOCs. diff --git a/drivers/phy/freescale/Makefile b/drivers/phy/freescale/Makefile index 1d02e3869b45..55d07c742ab0 100644 --- a/drivers/phy/freescale/Makefile +++ b/drivers/phy/freescale/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_PHY_FSL_IMX8MQ_USB) += phy-fsl-imx8mq-usb.o obj-$(CONFIG_PHY_MIXEL_MIPI_DPHY) += phy-fsl-imx8-mipi-dphy.o +obj-$(CONFIG_PHY_FSL_IMX8M_PCIE) += phy-fsl-imx8m-pcie.o diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c new file mode 100644 index 000000000000..f6502463d49a --- /dev/null +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c @@ -0,0 +1,236 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2021 NXP + */ + +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/delay.h> +#include <linux/mfd/syscon.h> +#include <linux/mfd/syscon/imx7-iomuxc-gpr.h> +#include <linux/module.h> +#include <linux/phy/phy.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/reset.h> +#include <dt-bindings/phy/phy-imx8-pcie.h> + +#define IMX8MM_PCIE_PHY_CMN_REG061 0x184 +#define ANA_PLL_CLK_OUT_TO_EXT_IO_EN BIT(0) +#define IMX8MM_PCIE_PHY_CMN_REG062 0x188 +#define ANA_PLL_CLK_OUT_TO_EXT_IO_SEL BIT(3) +#define IMX8MM_PCIE_PHY_CMN_REG063 0x18C +#define AUX_PLL_REFCLK_SEL_SYS_PLL GENMASK(7, 6) +#define IMX8MM_PCIE_PHY_CMN_REG064 0x190 +#define ANA_AUX_RX_TX_SEL_TX BIT(7) +#define ANA_AUX_RX_TERM_GND_EN BIT(3) +#define ANA_AUX_TX_TERM BIT(2) +#define IMX8MM_PCIE_PHY_CMN_REG065 0x194 +#define ANA_AUX_RX_TERM (BIT(7) | BIT(4)) +#define ANA_AUX_TX_LVL GENMASK(3, 0) +#define IMX8MM_PCIE_PHY_CMN_REG75 0x1D4 +#define PCIE_PHY_CMN_REG75_PLL_DONE 0x3 +#define PCIE_PHY_TRSV_REG5 0x414 +#define PCIE_PHY_TRSV_REG5_GEN1_DEEMP 0x2D +#define PCIE_PHY_TRSV_REG6 0x418 +#define PCIE_PHY_TRSV_REG6_GEN2_DEEMP 0xF + +#define IMX8MM_GPR_PCIE_REF_CLK_SEL GENMASK(25, 24) +#define IMX8MM_GPR_PCIE_REF_CLK_PLL FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3) +#define IMX8MM_GPR_PCIE_REF_CLK_EXT FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x2) +#define IMX8MM_GPR_PCIE_AUX_EN BIT(19) +#define IMX8MM_GPR_PCIE_CMN_RST BIT(18) +#define IMX8MM_GPR_PCIE_POWER_OFF BIT(17) +#define IMX8MM_GPR_PCIE_SSC_EN BIT(16) +#define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE BIT(9) + +struct imx8_pcie_phy { + void __iomem *base; + struct clk *clk; + struct phy *phy; + struct regmap *iomuxc_gpr; + struct reset_control *reset; + u32 refclk_pad_mode; + u32 tx_deemph_gen1; + u32 tx_deemph_gen2; + bool clkreq_unused; +}; + +static int imx8_pcie_phy_init(struct phy *phy) +{ + int ret; + u32 val, pad_mode; + struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); + + reset_control_assert(imx8_phy->reset); + + pad_mode = imx8_phy->refclk_pad_mode; + /* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */ + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE, + imx8_phy->clkreq_unused ? + 0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE); + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_AUX_EN, + IMX8MM_GPR_PCIE_AUX_EN); + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_POWER_OFF, 0); + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_SSC_EN, 0); + + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_REF_CLK_SEL, + pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ? + IMX8MM_GPR_PCIE_REF_CLK_EXT : + IMX8MM_GPR_PCIE_REF_CLK_PLL); + usleep_range(100, 200); + + /* Do the PHY common block reset */ + regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, + IMX8MM_GPR_PCIE_CMN_RST, + IMX8MM_GPR_PCIE_CMN_RST); + usleep_range(200, 500); + + if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT) { + /* Configure the pad as input */ + val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); + writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN, + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); + } else if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) { + /* Configure the PHY to output the refclock via pad */ + writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN, + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061); + writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL, + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062); + writel(AUX_PLL_REFCLK_SEL_SYS_PLL, + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063); + val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM; + writel(val | ANA_AUX_RX_TERM_GND_EN, + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064); + writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL, + imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065); + } + + /* Tune PHY de-emphasis setting to pass PCIe compliance. */ + if (imx8_phy->tx_deemph_gen1) + writel(imx8_phy->tx_deemph_gen1, + imx8_phy->base + PCIE_PHY_TRSV_REG5); + if (imx8_phy->tx_deemph_gen2) + writel(imx8_phy->tx_deemph_gen2, + imx8_phy->base + PCIE_PHY_TRSV_REG6); + + reset_control_deassert(imx8_phy->reset); + + /* Polling to check the phy is ready or not. */ + ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG75, + val, val == PCIE_PHY_CMN_REG75_PLL_DONE, + 10, 20000); + return ret; +} + +static int imx8_pcie_phy_power_on(struct phy *phy) +{ + struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); + + return clk_prepare_enable(imx8_phy->clk); +} + +static int imx8_pcie_phy_power_off(struct phy *phy) +{ + struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy); + + clk_disable_unprepare(imx8_phy->clk); + + return 0; +} + +static const struct phy_ops imx8_pcie_phy_ops = { + .init = imx8_pcie_phy_init, + .power_on = imx8_pcie_phy_power_on, + .power_off = imx8_pcie_phy_power_off, + .owner = THIS_MODULE, +}; + +static int imx8_pcie_phy_probe(struct platform_device *pdev) +{ + struct phy_provider *phy_provider; + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct imx8_pcie_phy *imx8_phy; + struct resource *res; + + imx8_phy = devm_kzalloc(dev, sizeof(*imx8_phy), GFP_KERNEL); + if (!imx8_phy) + return -ENOMEM; + + /* get PHY refclk pad mode */ + of_property_read_u32(np, "fsl,refclk-pad-mode", + &imx8_phy->refclk_pad_mode); + + if (of_property_read_u32(np, "fsl,tx-deemph-gen1", + &imx8_phy->tx_deemph_gen1)) + imx8_phy->tx_deemph_gen1 = 0; + + if (of_property_read_u32(np, "fsl,tx-deemph-gen2", + &imx8_phy->tx_deemph_gen2)) + imx8_phy->tx_deemph_gen2 = 0; + + if (of_property_read_bool(np, "fsl,clkreq-unsupported")) + imx8_phy->clkreq_unused = true; + else + imx8_phy->clkreq_unused = false; + + imx8_phy->clk = devm_clk_get(dev, "ref"); + if (IS_ERR(imx8_phy->clk)) { + dev_err(dev, "failed to get imx pcie phy clock\n"); + return PTR_ERR(imx8_phy->clk); + } + + /* Grab GPR config register range */ + imx8_phy->iomuxc_gpr = + syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); + if (IS_ERR(imx8_phy->iomuxc_gpr)) { + dev_err(dev, "unable to find iomuxc registers\n"); + return PTR_ERR(imx8_phy->iomuxc_gpr); + } + + imx8_phy->reset = devm_reset_control_get_exclusive(dev, "pciephy"); + if (IS_ERR(imx8_phy->reset)) { + dev_err(dev, "Failed to get PCIEPHY reset control\n"); + return PTR_ERR(imx8_phy->reset); + } + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + imx8_phy->base = devm_ioremap_resource(dev, res); + if (IS_ERR(imx8_phy->base)) + return PTR_ERR(imx8_phy->base); + + imx8_phy->phy = devm_phy_create(dev, NULL, &imx8_pcie_phy_ops); + if (IS_ERR(imx8_phy->phy)) + return PTR_ERR(imx8_phy->phy); + + phy_set_drvdata(imx8_phy->phy, imx8_phy); + + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id imx8_pcie_phy_of_match[] = { + {.compatible = "fsl,imx8mm-pcie-phy",}, + { }, +}; +MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match); + +static struct platform_driver imx8_pcie_phy_driver = { + .probe = imx8_pcie_phy_probe, + .driver = { + .name = "imx8-pcie-phy", + .of_match_table = imx8_pcie_phy_of_match, + } +}; +module_platform_driver(imx8_pcie_phy_driver); + +MODULE_DESCRIPTION("FSL IMX8 PCIE PHY driver"); +MODULE_LICENSE("GPL v2");