Message ID | 20211215012543.18689-1-haochen.jiang@intel.com |
---|---|
State | New |
Headers | show |
Series | [i386,avx512] Add combine splitter to transform vpternlogd/vpcmpeqd/vpxor/vblendvps to vblendvps for ~op0 | expand |
On Wed, Dec 15, 2021 at 9:26 AM Haochen Jiang via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > Hi all, > > This patch fix the regression previously reported on the combine splitter under '-m32 -march=cascadelake' options. > > Regtested on x86_64-pc-linux-gnu. Ok. > > BRs, > Haochen > > gcc/ChangeLog: > > PR target/100738 > * config/i386/sse.md (*avx_cmp<mode>3_lt, *avx_cmp<mode>3_ltint): > Remove MEM_P restriction and add force_reg for operands[2]. > (*avx_cmp<mode>3_ltint_not): Add new define_insn_and_split. > > gcc/testsuite/ChangeLog: > > PR target/100738 > * g++.target/i386/avx512vl-pr100738-1.C: New test. > --- > gcc/config/i386/sse.md | 44 +++++++++++++++++-- > .../g++.target/i386/avx512vl-pr100738-1.C | 8 ++++ > 2 files changed, 48 insertions(+), 4 deletions(-) > create mode 100755 gcc/testsuite/g++.target/i386/avx512vl-pr100738-1.C > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 5421fb51684..8ec9fb075d0 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -3528,8 +3528,7 @@ > UNSPEC_PCMP)))] > "TARGET_AVX512VL && ix86_pre_reload_split () > /* LT or GE 0 */ > - && ((INTVAL (operands[5]) == 1 && !MEM_P (operands[2])) > - || (INTVAL (operands[5]) == 5 && !MEM_P (operands[1])))" > + && ((INTVAL (operands[5]) == 1) || (INTVAL (operands[5]) == 5))" > "#" > "&& 1" > [(set (match_dup 0) > @@ -3543,6 +3542,7 @@ > { > if (INTVAL (operands[5]) == 5) > std::swap (operands[1], operands[2]); > + operands[2] = force_reg (<MODE>mode, operands[2]); > }) > > (define_insn_and_split "*avx_cmp<mode>3_ltint" > @@ -3557,8 +3557,7 @@ > UNSPEC_PCMP)))] > "TARGET_AVX512VL && ix86_pre_reload_split () > /* LT or GE 0 */ > - && ((INTVAL (operands[5]) == 1 && !MEM_P (operands[2])) > - || (INTVAL (operands[5]) == 5 && !MEM_P (operands[1])))" > + && ((INTVAL (operands[5]) == 1) || (INTVAL (operands[5]) == 5))" > "#" > "&& 1" > [(set (match_dup 0) > @@ -3575,7 +3574,44 @@ > std::swap (operands[1], operands[2]); > operands[0] = gen_lowpart (<ssebytemode>mode, operands[0]); > operands[1] = gen_lowpart (<ssebytemode>mode, operands[1]); > + operands[2] = force_reg (<ssebytemode>mode, > + gen_lowpart (<ssebytemode>mode, operands[2])); > +}) > + > +(define_insn_and_split "*avx_cmp<mode>3_ltint_not" > + [(set (match_operand:VI48_AVX 0 "register_operand") > + (vec_merge:VI48_AVX > + (match_operand:VI48_AVX 1 "vector_operand") > + (match_operand:VI48_AVX 2 "vector_operand") > + (unspec:<avx512fmaskmode> > + [(subreg:VI48_AVX > + (not:<ssebytemode> > + (match_operand:<ssebytemode> 3 "vector_operand")) 0) > + (match_operand:VI48_AVX 4 "const0_operand") > + (match_operand:SI 5 "const_0_to_7_operand")] > + UNSPEC_PCMP)))] > + "TARGET_AVX512VL && ix86_pre_reload_split () > + /* not LT or GE 0 */ > + && ((INTVAL (operands[5]) == 1) || (INTVAL (operands[5]) == 5))" > + "#" > + "&& 1" > + [(set (match_dup 0) > + (unspec:<ssebytemode> > + [(match_dup 1) > + (match_dup 2) > + (subreg:<ssebytemode> > + (lt:VI48_AVX > + (match_dup 3) > + (match_dup 4)) 0)] > + UNSPEC_BLENDV))] > +{ > + if (INTVAL (operands[5]) == 5) > + std::swap (operands[1], operands[2]); > + operands[0] = gen_lowpart (<ssebytemode>mode, operands[0]); > + operands[1] = force_reg (<ssebytemode>mode, > + gen_lowpart (<ssebytemode>mode, operands[1])); > operands[2] = gen_lowpart (<ssebytemode>mode, operands[2]); > + operands[3] = lowpart_subreg (<MODE>mode, operands[3], <ssebytemode>mode); > }) > > (define_insn "avx_vmcmp<mode>3" > diff --git a/gcc/testsuite/g++.target/i386/avx512vl-pr100738-1.C b/gcc/testsuite/g++.target/i386/avx512vl-pr100738-1.C > new file mode 100755 > index 00000000000..ac4d62b94d1 > --- /dev/null > +++ b/gcc/testsuite/g++.target/i386/avx512vl-pr100738-1.C > @@ -0,0 +1,8 @@ > +/* { dg-do compile } */ > +/* { dg-options "-Ofast -march=cascadelake" } */ > +/* { dg-final {scan-assembler-times "vblendvps\[ \\t\]" 2 } } */ > +/* { dg-final {scan-assembler-not "vpcmpeqd\[ \\t\]" } } */ > +/* { dg-final {scan-assembler-not "vpxor\[ \\t\]" } } */ > +/* { dg-final {scan-assembler-not "vpternlogd\[ \\t\]" } } */ > + > +#include "pr100738-1.C" > -- > 2.18.1 >
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 5421fb51684..8ec9fb075d0 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -3528,8 +3528,7 @@ UNSPEC_PCMP)))] "TARGET_AVX512VL && ix86_pre_reload_split () /* LT or GE 0 */ - && ((INTVAL (operands[5]) == 1 && !MEM_P (operands[2])) - || (INTVAL (operands[5]) == 5 && !MEM_P (operands[1])))" + && ((INTVAL (operands[5]) == 1) || (INTVAL (operands[5]) == 5))" "#" "&& 1" [(set (match_dup 0) @@ -3543,6 +3542,7 @@ { if (INTVAL (operands[5]) == 5) std::swap (operands[1], operands[2]); + operands[2] = force_reg (<MODE>mode, operands[2]); }) (define_insn_and_split "*avx_cmp<mode>3_ltint" @@ -3557,8 +3557,7 @@ UNSPEC_PCMP)))] "TARGET_AVX512VL && ix86_pre_reload_split () /* LT or GE 0 */ - && ((INTVAL (operands[5]) == 1 && !MEM_P (operands[2])) - || (INTVAL (operands[5]) == 5 && !MEM_P (operands[1])))" + && ((INTVAL (operands[5]) == 1) || (INTVAL (operands[5]) == 5))" "#" "&& 1" [(set (match_dup 0) @@ -3575,7 +3574,44 @@ std::swap (operands[1], operands[2]); operands[0] = gen_lowpart (<ssebytemode>mode, operands[0]); operands[1] = gen_lowpart (<ssebytemode>mode, operands[1]); + operands[2] = force_reg (<ssebytemode>mode, + gen_lowpart (<ssebytemode>mode, operands[2])); +}) + +(define_insn_and_split "*avx_cmp<mode>3_ltint_not" + [(set (match_operand:VI48_AVX 0 "register_operand") + (vec_merge:VI48_AVX + (match_operand:VI48_AVX 1 "vector_operand") + (match_operand:VI48_AVX 2 "vector_operand") + (unspec:<avx512fmaskmode> + [(subreg:VI48_AVX + (not:<ssebytemode> + (match_operand:<ssebytemode> 3 "vector_operand")) 0) + (match_operand:VI48_AVX 4 "const0_operand") + (match_operand:SI 5 "const_0_to_7_operand")] + UNSPEC_PCMP)))] + "TARGET_AVX512VL && ix86_pre_reload_split () + /* not LT or GE 0 */ + && ((INTVAL (operands[5]) == 1) || (INTVAL (operands[5]) == 5))" + "#" + "&& 1" + [(set (match_dup 0) + (unspec:<ssebytemode> + [(match_dup 1) + (match_dup 2) + (subreg:<ssebytemode> + (lt:VI48_AVX + (match_dup 3) + (match_dup 4)) 0)] + UNSPEC_BLENDV))] +{ + if (INTVAL (operands[5]) == 5) + std::swap (operands[1], operands[2]); + operands[0] = gen_lowpart (<ssebytemode>mode, operands[0]); + operands[1] = force_reg (<ssebytemode>mode, + gen_lowpart (<ssebytemode>mode, operands[1])); operands[2] = gen_lowpart (<ssebytemode>mode, operands[2]); + operands[3] = lowpart_subreg (<MODE>mode, operands[3], <ssebytemode>mode); }) (define_insn "avx_vmcmp<mode>3" diff --git a/gcc/testsuite/g++.target/i386/avx512vl-pr100738-1.C b/gcc/testsuite/g++.target/i386/avx512vl-pr100738-1.C new file mode 100755 index 00000000000..ac4d62b94d1 --- /dev/null +++ b/gcc/testsuite/g++.target/i386/avx512vl-pr100738-1.C @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-Ofast -march=cascadelake" } */ +/* { dg-final {scan-assembler-times "vblendvps\[ \\t\]" 2 } } */ +/* { dg-final {scan-assembler-not "vpcmpeqd\[ \\t\]" } } */ +/* { dg-final {scan-assembler-not "vpxor\[ \\t\]" } } */ +/* { dg-final {scan-assembler-not "vpternlogd\[ \\t\]" } } */ + +#include "pr100738-1.C"