Message ID | 20211214051723.62082-1-hongtao.liu@intel.com |
---|---|
State | New |
Headers | show |
Series | [Gimple] Fix ICE. [PR103682] | expand |
On 12/13/2021 10:17 PM, liuhongt via Gcc-patches wrote: >> This testcase should just go in gcc.c-torture/compile and remove the >> dg-options too. >> The main reason there is nothing specific to x86 here. >> > Thanks, here's the updated patch. > > > Check is_gimple_assign before gimple_assign_rhs_code. > > gcc/ChangeLog: > > PR target/103682 > * tree-ssa-ccp.c (optimize_atomic_bit_test_and): Check > is_gimple_assign before gimple_assign_rhs_code. > > gcc/testsuite/ChangeLog: > > * gcc.c-torture/compile/pr103682.c: New test. OK jeff
diff --git a/gcc/testsuite/gcc.c-torture/compile/pr103682.c b/gcc/testsuite/gcc.c-torture/compile/pr103682.c new file mode 100644 index 00000000000..5ee4b21f7e6 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/compile/pr103682.c @@ -0,0 +1,3 @@ +int bug(unsigned *ready, unsigned u) { + return __atomic_fetch_and (ready, ~u, 0) & u; +} diff --git a/gcc/tree-ssa-ccp.c b/gcc/tree-ssa-ccp.c index 9e12da8f011..a5b1f60f979 100644 --- a/gcc/tree-ssa-ccp.c +++ b/gcc/tree-ssa-ccp.c @@ -3703,8 +3703,8 @@ optimize_atomic_bit_test_and (gimple_stmt_iterator *gsip, g = SSA_NAME_DEF_STMT (mask); } - rhs_code = gimple_assign_rhs_code (g); - if (rhs_code != LSHIFT_EXPR + if (!is_gimple_assign (g) + || gimple_assign_rhs_code (g) != LSHIFT_EXPR || !integer_onep (gimple_assign_rhs1 (g))) return; bit = gimple_assign_rhs2 (g);