| Message ID | 20211128131853.15125-1-aford173@gmail.com |
|---|---|
| Headers | show |
| Series | arm64: imx8mn: Enable more imx8m Nano functions | expand |
On Sun, Nov 28, 2021 at 7:19 AM Adam Ford <aford173@gmail.com> wrote: > > The i.MX8M Nano is similar to the i.MX8M Mini in some ways, but very > different in others. With the blk-ctrl driver for Mini in place, > this series expands the blk-ctrl driver to support the Nano which > opens the door for additional functions in the future. As part of > this series, it also addresses some issues in the GPCv2 driver and > finally adds support for enabling USB and GPU. > > V4: Rebase on top of [1] which fixes hangs caused from CSI and DSI reset > and add the same fixes for CSI and DSI to the Nano > V3: Fixes an the yaml example > V2: Fixes the clock count in the blk-ctrl > > [1] - https://www.spinics.net/lists/arm-kernel/msg936266.html > Shawn, This series should apply cleanly against your tree now that [1] has been applied to your tree. Should I submit this a resend or are you able to test the build now? adam > Adam Ford (9): > soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled > soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn > dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains > dt-bindings: soc: add binding for i.MX8MN DISP blk-ctrl > soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl > arm64: dts: imx8mn: add GPC node > arm64: dts: imx8mn: put USB controller into power-domains > arm64: dts: imx8mn: add DISP blk-ctrl > arm64: dts: imx8mn: Enable GPU > > .../soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml | 97 +++++++++++++++++ > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 103 ++++++++++++++++++ > drivers/soc/imx/gpcv2.c | 26 +++++ > drivers/soc/imx/imx8m-blk-ctrl.c | 77 ++++++++++++- > include/dt-bindings/power/imx8mn-power.h | 5 + > 5 files changed, 307 insertions(+), 1 deletion(-) > create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml > > -- > 2.32.0 >
On Mon, Dec 13, 2021 at 09:03:06PM -0600, Adam Ford wrote: > On Sun, Nov 28, 2021 at 7:19 AM Adam Ford <aford173@gmail.com> wrote: > > > > The i.MX8M Nano is similar to the i.MX8M Mini in some ways, but very > > different in others. With the blk-ctrl driver for Mini in place, > > this series expands the blk-ctrl driver to support the Nano which > > opens the door for additional functions in the future. As part of > > this series, it also addresses some issues in the GPCv2 driver and > > finally adds support for enabling USB and GPU. > > > > V4: Rebase on top of [1] which fixes hangs caused from CSI and DSI reset > > and add the same fixes for CSI and DSI to the Nano > > V3: Fixes an the yaml example > > V2: Fixes the clock count in the blk-ctrl > > > > [1] - https://www.spinics.net/lists/arm-kernel/msg936266.html > > > > Shawn, > > This series should apply cleanly against your tree now that [1] has > been applied to your tree. Should I submit this a resend or are you > able to test the build now? I haven't seen any comments on this series from Lucas. Shawn
On Sun, Nov 28, 2021 at 7:19 AM Adam Ford <aford173@gmail.com> wrote: > > This adds the description for the i.MX8MN disp blk-ctrl. > > Signed-off-by: Adam Ford <aford173@gmail.com> Lucas, Is there any chance you could give this series some feedback? In order to get more functionality on the Nano, we need the blk-ctrl on Nano working. thanks, adam > --- > drivers/soc/imx/imx8m-blk-ctrl.c | 77 +++++++++++++++++++++++++++++++- > 1 file changed, 76 insertions(+), 1 deletion(-) > > diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c > index c2f076b56e24..511e74f0db8a 100644 > --- a/drivers/soc/imx/imx8m-blk-ctrl.c > +++ b/drivers/soc/imx/imx8m-blk-ctrl.c > @@ -14,6 +14,7 @@ > #include <linux/clk.h> > > #include <dt-bindings/power/imx8mm-power.h> > +#include <dt-bindings/power/imx8mn-power.h> > > #define BLK_SFT_RSTN 0x0 > #define BLK_CLK_EN 0x4 > @@ -517,6 +518,77 @@ static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = { > .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data), > }; > > + > +static int imx8mn_disp_power_notifier(struct notifier_block *nb, > + unsigned long action, void *data) > +{ > + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, > + power_nb); > + > + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) > + return NOTIFY_OK; > + > + /* Enable bus clock and deassert bus reset */ > + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8)); > + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8)); > + > + /* > + * On power up we have no software backchannel to the GPC to > + * wait for the ADB handshake to happen, so we just delay for a > + * bit. On power down the GPC driver waits for the handshake. > + */ > + if (action == GENPD_NOTIFY_ON) > + udelay(5); > + > + > + return NOTIFY_OK; > +} > + > +static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = { > + [IMX8MN_DISPBLK_PD_MIPI_DSI] = { > + .name = "dispblk-mipi-dsi", > + .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", }, > + .num_clks = 2, > + .gpc_name = "mipi-dsi", > + .rst_mask = BIT(0) | BIT(1), > + .clk_mask = BIT(0) | BIT(1), > + .mipi_phy_rst_mask = BIT(17), > + }, > + [IMX8MN_DISPBLK_PD_MIPI_CSI] = { > + .name = "dispblk-mipi-csi", > + .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" }, > + .num_clks = 2, > + .gpc_name = "mipi-csi", > + .rst_mask = BIT(2) | BIT(3), > + .clk_mask = BIT(2) | BIT(3), > + .mipi_phy_rst_mask = BIT(16), > + }, > + [IMX8MN_DISPBLK_PD_LCDIF] = { > + .name = "dispblk-lcdif", > + .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", }, > + .num_clks = 3, > + .gpc_name = "lcdif", > + .rst_mask = BIT(4) | BIT(5), > + .clk_mask = BIT(4) | BIT(5), > + }, > + [IMX8MN_DISPBLK_PD_ISI] = { > + .name = "dispblk-isi", > + .clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root", > + "disp_apb_root"}, > + .num_clks = 4, > + .gpc_name = "isi", > + .rst_mask = BIT(6) | BIT(7), > + .clk_mask = BIT(6) | BIT(7), > + }, > +}; > + > +static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = { > + .max_reg = 0x84, > + .power_notifier_fn = imx8mn_disp_power_notifier, > + .domains = imx8mn_disp_blk_ctl_domain_data, > + .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data), > +}; > + > static const struct of_device_id imx8m_blk_ctrl_of_match[] = { > { > .compatible = "fsl,imx8mm-vpu-blk-ctrl", > @@ -524,7 +596,10 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = { > }, { > .compatible = "fsl,imx8mm-disp-blk-ctrl", > .data = &imx8mm_disp_blk_ctl_dev_data > - } ,{ > + }, { > + .compatible = "fsl,imx8mn-disp-blk-ctrl", > + .data = &imx8mn_disp_blk_ctl_dev_data > + }, { > /* Sentinel */ > } > }; > -- > 2.32.0 >
Am Sonntag, dem 28.11.2021 um 07:18 -0600 schrieb Adam Ford: > Like the i.MX8MM, keep the gpumix clocks running when the > domain is active. > > Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> > --- > drivers/soc/imx/gpcv2.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c > index 8176380b02e6..a0eab9f41a71 100644 > --- a/drivers/soc/imx/gpcv2.c > +++ b/drivers/soc/imx/gpcv2.c > @@ -841,6 +841,7 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = { > .hskack = IMX8MN_GPUMIX_HSK_PWRDNACKN, > }, > .pgc = BIT(IMX8MN_PGC_GPUMIX), > + .keep_clocks = true, > }, > }; > > -- > 2.32.0 >
Am Sonntag, dem 28.11.2021 um 07:18 -0600 schrieb Adam Ford: > The dispmix will be needed for the blkctl driver, so add it > to the gpcv2. > > Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> > --- > drivers/soc/imx/gpcv2.c | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c > index a0eab9f41a71..3e59d479d001 100644 > --- a/drivers/soc/imx/gpcv2.c > +++ b/drivers/soc/imx/gpcv2.c > @@ -843,6 +843,31 @@ static const struct imx_pgc_domain imx8mn_pgc_domains[] = { > .pgc = BIT(IMX8MN_PGC_GPUMIX), > .keep_clocks = true, > }, > + > + [IMX8MN_POWER_DOMAIN_DISPMIX] = { > + .genpd = { > + .name = "dispmix", > + }, > + .bits = { > + .pxx = IMX8MN_DISPMIX_SW_Pxx_REQ, > + .map = IMX8MN_DISPMIX_A53_DOMAIN, > + .hskreq = IMX8MN_DISPMIX_HSK_PWRDNREQN, > + .hskack = IMX8MN_DISPMIX_HSK_PWRDNACKN, > + }, > + .pgc = BIT(IMX8MN_PGC_DISPMIX), > + .keep_clocks = true, > + }, > + > + [IMX8MN_POWER_DOMAIN_MIPI] = { > + .genpd = { > + .name = "mipi", > + }, > + .bits = { > + .pxx = IMX8MN_MIPI_SW_Pxx_REQ, > + .map = IMX8MN_MIPI_A53_DOMAIN, > + }, > + .pgc = BIT(IMX8MN_PGC_MIPI), > + }, > }; > > static const struct regmap_range imx8mn_yes_ranges[] = { > -- > 2.32.0 >
Am Sonntag, dem 28.11.2021 um 07:18 -0600 schrieb Adam Ford: > This adds the description for the i.MX8MN disp blk-ctrl. > > Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> > --- > drivers/soc/imx/imx8m-blk-ctrl.c | 77 +++++++++++++++++++++++++++++++- > 1 file changed, 76 insertions(+), 1 deletion(-) > > diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c > index c2f076b56e24..511e74f0db8a 100644 > --- a/drivers/soc/imx/imx8m-blk-ctrl.c > +++ b/drivers/soc/imx/imx8m-blk-ctrl.c > @@ -14,6 +14,7 @@ > #include <linux/clk.h> > > #include <dt-bindings/power/imx8mm-power.h> > +#include <dt-bindings/power/imx8mn-power.h> > > #define BLK_SFT_RSTN 0x0 > #define BLK_CLK_EN 0x4 > @@ -517,6 +518,77 @@ static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = { > .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data), > }; > > + > +static int imx8mn_disp_power_notifier(struct notifier_block *nb, > + unsigned long action, void *data) > +{ > + struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl, > + power_nb); > + > + if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF) > + return NOTIFY_OK; > + > + /* Enable bus clock and deassert bus reset */ > + regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8)); > + regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8)); > + > + /* > + * On power up we have no software backchannel to the GPC to > + * wait for the ADB handshake to happen, so we just delay for a > + * bit. On power down the GPC driver waits for the handshake. > + */ > + if (action == GENPD_NOTIFY_ON) > + udelay(5); > + > + > + return NOTIFY_OK; > +} > + > +static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = { > + [IMX8MN_DISPBLK_PD_MIPI_DSI] = { > + .name = "dispblk-mipi-dsi", > + .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", }, > + .num_clks = 2, > + .gpc_name = "mipi-dsi", > + .rst_mask = BIT(0) | BIT(1), > + .clk_mask = BIT(0) | BIT(1), > + .mipi_phy_rst_mask = BIT(17), > + }, > + [IMX8MN_DISPBLK_PD_MIPI_CSI] = { > + .name = "dispblk-mipi-csi", > + .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" }, > + .num_clks = 2, > + .gpc_name = "mipi-csi", > + .rst_mask = BIT(2) | BIT(3), > + .clk_mask = BIT(2) | BIT(3), > + .mipi_phy_rst_mask = BIT(16), > + }, > + [IMX8MN_DISPBLK_PD_LCDIF] = { > + .name = "dispblk-lcdif", > + .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", }, > + .num_clks = 3, > + .gpc_name = "lcdif", > + .rst_mask = BIT(4) | BIT(5), > + .clk_mask = BIT(4) | BIT(5), > + }, > + [IMX8MN_DISPBLK_PD_ISI] = { > + .name = "dispblk-isi", > + .clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root", > + "disp_apb_root"}, > + .num_clks = 4, > + .gpc_name = "isi", > + .rst_mask = BIT(6) | BIT(7), > + .clk_mask = BIT(6) | BIT(7), > + }, > +}; > + > +static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = { > + .max_reg = 0x84, > + .power_notifier_fn = imx8mn_disp_power_notifier, > + .domains = imx8mn_disp_blk_ctl_domain_data, > + .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data), > +}; > + > static const struct of_device_id imx8m_blk_ctrl_of_match[] = { > { > .compatible = "fsl,imx8mm-vpu-blk-ctrl", > @@ -524,7 +596,10 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = { > }, { > .compatible = "fsl,imx8mm-disp-blk-ctrl", > .data = &imx8mm_disp_blk_ctl_dev_data > - } ,{ > + }, { > + .compatible = "fsl,imx8mn-disp-blk-ctrl", > + .data = &imx8mn_disp_blk_ctl_dev_data > + }, { > /* Sentinel */ > } > }; > -- > 2.32.0 >
Am Sonntag, dem 28.11.2021 um 07:18 -0600 schrieb Adam Ford: > Add the DT node for the GPC, including all the PGC power domains, > some of them are not fully functional yet, as they require interaction > with the blk-ctrls to properly power up/down the peripherals. > > Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> > --- > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 49 +++++++++++++++++++++++ > 1 file changed, 49 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > index ba23b416b5e6..ef1699a9cd7d 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -4,6 +4,8 @@ > */ > > #include <dt-bindings/clock/imx8mn-clock.h> > +#include <dt-bindings/power/imx8mn-power.h> > +#include <dt-bindings/reset/imx8mq-reset.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/input/input.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > @@ -640,6 +642,53 @@ src: reset-controller@30390000 { > interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; > #reset-cells = <1>; > }; > + > + gpc: gpc@303a0000 { > + compatible = "fsl,imx8mn-gpc"; > + reg = <0x303a0000 0x10000>; > + interrupt-parent = <&gic>; > + interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; > + > + pgc { > + #address-cells = <1>; > + #size-cells = <0>; > + > + pgc_hsiomix: power-domain@0 { > + #power-domain-cells = <0>; > + reg = <IMX8MN_POWER_DOMAIN_HSIOMIX>; > + clocks = <&clk IMX8MN_CLK_USB_BUS>; > + }; > + > + pgc_otg1: power-domain@1 { > + #power-domain-cells = <0>; > + reg = <IMX8MN_POWER_DOMAIN_OTG1>; > + power-domains = <&pgc_hsiomix>; > + }; > + > + pgc_gpumix: power-domain@2 { > + #power-domain-cells = <0>; > + reg = <IMX8MN_POWER_DOMAIN_GPUMIX>; > + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, > + <&clk IMX8MN_CLK_GPU_SHADER>, > + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MN_CLK_GPU_AHB>; > + resets = <&src IMX8MQ_RESET_GPU_RESET>; > + }; > + > + pgc_dispmix: power-domain@3 { > + #power-domain-cells = <0>; > + reg = <IMX8MN_POWER_DOMAIN_DISPMIX>; > + clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>, > + <&clk IMX8MN_CLK_DISP_APB_ROOT>; > + }; > + > + pgc_mipi: power-domain@4 { > + #power-domain-cells = <0>; > + reg = <IMX8MN_POWER_DOMAIN_MIPI>; > + power-domains = <&pgc_dispmix>; > + }; > + }; > + }; > }; > > aips2: bus@30400000 { > -- > 2.32.0 >
Am Sonntag, dem 28.11.2021 um 07:18 -0600 schrieb Adam Ford: > Add the DT node for the DISP blk-ctrl. With this in place the > display/mipi power domains should be functional. > > Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Lucas Stach <l.stach@pengutronix.de> > --- > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 28 +++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > index 902d5725dc55..d8726d0ce326 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -1039,6 +1039,34 @@ aips4: bus@32c00000 { > #size-cells = <1>; > ranges; > > + disp_blk_ctrl: blk-ctrl@32e28000 { > + compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon"; > + reg = <0x32e28000 0x100>; > + power-domains = <&pgc_dispmix>, <&pgc_dispmix>, > + <&pgc_dispmix>, <&pgc_mipi>, > + <&pgc_mipi>; > + power-domain-names = "bus", "isi", > + "lcdif", "mipi-dsi", > + "mipi-csi"; > + clocks = <&clk IMX8MN_CLK_DISP_AXI>, > + <&clk IMX8MN_CLK_DISP_APB>, > + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, > + <&clk IMX8MN_CLK_DISP_APB_ROOT>, > + <&clk IMX8MN_CLK_DISP_AXI_ROOT>, > + <&clk IMX8MN_CLK_DISP_APB_ROOT>, > + <&clk IMX8MN_CLK_DISP_PIXEL_ROOT>, > + <&clk IMX8MN_CLK_DSI_CORE>, > + <&clk IMX8MN_CLK_DSI_PHY_REF>, > + <&clk IMX8MN_CLK_CSI1_PHY_REF>, > + <&clk IMX8MN_CLK_CAMERA_PIXEL_ROOT>; > + clock-names = "disp_axi", "disp_apb", > + "disp_axi_root", "disp_apb_root", > + "lcdif-axi", "lcdif-apb", "lcdif-pix", > + "dsi-pclk", "dsi-ref", > + "csi-aclk", "csi-pclk"; > + #power-domain-cells = <1>; > + }; > + > usbotg1: usb@32e40000 { > compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb"; > reg = <0x32e40000 0x200>; > -- > 2.32.0 >
Am Sonntag, dem 28.11.2021 um 07:18 -0600 schrieb Adam Ford: > The i.MX8M-Nano features a GC7000. The Etnaviv driver detects it as: > > etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6203 > > Signed-off-by: Adam Ford <aford173@gmail.com> > --- > arch/arm64/boot/dts/freescale/imx8mn.dtsi | 25 +++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > index d8726d0ce326..5b8f8488e362 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -1117,6 +1117,31 @@ gpmi: nand-controller@33002000 { > status = "disabled"; > }; > > + gpu: gpu@38000000 { > + compatible = "vivante,gc"; > + reg = <0x38000000 0x8000>; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&clk IMX8MN_CLK_GPU_AHB>, > + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MN_CLK_GPU_CORE_ROOT>, > + <&clk IMX8MN_CLK_GPU_SHADER>; > + clock-names = "reg", "bus", "core", "shader"; > + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>, > + <&clk IMX8MN_CLK_GPU_SHADER>, > + <&clk IMX8MN_CLK_GPU_AXI>, > + <&clk IMX8MN_CLK_GPU_AHB>, > + <&clk IMX8MN_GPU_PLL>, > + <&clk IMX8MN_CLK_GPU_CORE>, > + <&clk IMX8MN_CLK_GPU_SHADER>; This repeated CORE and SHADER clock looks odd. Wouldn't it be possible to avoid this by reordering the assigned-clocks? Regards, Lucas > + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, > + <&clk IMX8MN_GPU_PLL_OUT>, > + <&clk IMX8MN_SYS_PLL1_800M>, > + <&clk IMX8MN_SYS_PLL1_800M>; > + assigned-clock-rates = <0>, <0>, <800000000>, <400000000>, <1200000000>, > + <400000000>, <400000000>; > + power-domains = <&pgc_gpumix>; > + }; > + > gic: interrupt-controller@38800000 { > compatible = "arm,gic-v3"; > reg = <0x38800000 0x10000>, > -- > 2.32.0 >
The i.MX8M Nano is similar to the i.MX8M Mini in some ways, but very different in others. With the blk-ctrl driver for Mini in place, this series expands the blk-ctrl driver to support the Nano which opens the door for additional functions in the future. As part of this series, it also addresses some issues in the GPCv2 driver and finally adds support for enabling USB and GPU. V4: Rebase on top of [1] which fixes hangs caused from CSI and DSI reset and add the same fixes for CSI and DSI to the Nano V3: Fixes an the yaml example V2: Fixes the clock count in the blk-ctrl [1] - https://www.spinics.net/lists/arm-kernel/msg936266.html Adam Ford (9): soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains dt-bindings: soc: add binding for i.MX8MN DISP blk-ctrl soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl arm64: dts: imx8mn: add GPC node arm64: dts: imx8mn: put USB controller into power-domains arm64: dts: imx8mn: add DISP blk-ctrl arm64: dts: imx8mn: Enable GPU .../soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml | 97 +++++++++++++++++ arch/arm64/boot/dts/freescale/imx8mn.dtsi | 103 ++++++++++++++++++ drivers/soc/imx/gpcv2.c | 26 +++++ drivers/soc/imx/imx8m-blk-ctrl.c | 77 ++++++++++++- include/dt-bindings/power/imx8mn-power.h | 5 + 5 files changed, 307 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml -- 2.32.0