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[3/4] target/ppc: fix xscvqpdp register access

Message ID 20211210141347.38603-4-victor.colombo@eldorado.org.br
State Superseded
Headers show
Series target/ppc: Fix VSX instructions register access | expand

Commit Message

Víctor Colombo Dec. 10, 2021, 2:13 p.m. UTC 
From: Matheus Ferst <matheus.ferst@eldorado.org.br>

This instruction has VRT and VRB fields instead of T/TX and B/BX.

Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
 target/ppc/translate/vsx-impl.c.inc | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

Comments

Richard Henderson Dec. 11, 2021, 5:05 p.m. UTC | #1 
On 12/10/21 6:13 AM, Victor Colombo wrote:
> From: Matheus Ferst<matheus.ferst@eldorado.org.br>
> 
> This instruction has VRT and VRB fields instead of T/TX and B/BX.
> 
> Signed-off-by: Matheus Ferst<matheus.ferst@eldorado.org.br>
> ---
>   target/ppc/translate/vsx-impl.c.inc | 5 +++--
>   1 file changed, 3 insertions(+), 2 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc
index e2447750dd..ab5cb21f13 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -913,8 +913,9 @@  static void gen_xscvqpdp(DisasContext *ctx)
         return;
     }
     opc = tcg_const_i32(ctx->opcode);
-    xt = gen_vsr_ptr(xT(ctx->opcode));
-    xb = gen_vsr_ptr(xB(ctx->opcode));
+
+    xt = gen_vsr_ptr(rD(ctx->opcode) + 32);
+    xb = gen_vsr_ptr(rB(ctx->opcode) + 32);
     gen_helper_xscvqpdp(cpu_env, opc, xt, xb);
     tcg_temp_free_i32(opc);
     tcg_temp_free_ptr(xt);