[V2,0/9] arm64: imx8mn: Enable additional power domains and peripherals

The blk-ctrl and the GPCv2 in the i.MX8MN is similar but slightly different to that
of the i.MX8MM.  This series is based on work from Lucas Stach for i.MX8MM, but
adapted for i.MX8MN.  With the additional power domains and blk-ctrl enabled,
additional peripherals like gpu and USB can be enabled.

V2:  Add mising patches for expanding GPCv2 which are necessary
       to make the blk-ctl operate.
     Fix clk names
     Fix missing references to structures in blk-ctl driver to link
       them to the device tree.

Adam Ford (9):
  soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled
  soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn
  dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains
  dt-bindings: soc: add binding for i.MX8MN DISP blk-ctrl
  soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl
  arm64: dts: imx8mn: add GPC node
  arm64: dts: imx8mn: put USB controller into power-domains
  arm64: dts: imx8mn: add DISP blk-ctrl
  arm64: dts: imx8mn: Enable GPU

 .../soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml     |  97 +++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8mn.dtsi     | 103 ++++++++++++++++++
 drivers/soc/imx/gpcv2.c                       |  26 +++++
 drivers/soc/imx/imx8m-blk-ctrl.c              |  75 ++++++++++++-
 include/dt-bindings/power/imx8mn-power.h      |   5 +
 5 files changed, 305 insertions(+), 1 deletion(-)
 create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml

On Sat, Oct 9, 2021 at 11:27 AM Adam Ford <aford173@gmail.com> wrote:
>
> This adds the description for the i.MX8MN disp blk-ctrl.
>
> Signed-off-by: Adam Ford <aford173@gmail.com>
> ---

Does anyone from NXP have any feedback on this?
I tried to look at the ISI driver and power domain and understand it,
but it's not present in the 8mm, so I went off my best understanding
of the datasheet.

adam

>  drivers/soc/imx/imx8m-blk-ctrl.c | 75 +++++++++++++++++++++++++++++++-
>  1 file changed, 74 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/imx/imx8m-blk-ctrl.c b/drivers/soc/imx/imx8m-blk-ctrl.c
> index e172d295c441..8d3bf7690383 100644
> --- a/drivers/soc/imx/imx8m-blk-ctrl.c
> +++ b/drivers/soc/imx/imx8m-blk-ctrl.c
> @@ -14,6 +14,7 @@
>  #include <linux/clk.h>
>
>  #include <dt-bindings/power/imx8mm-power.h>
> +#include <dt-bindings/power/imx8mn-power.h>
>
>  #define BLK_SFT_RSTN   0x0
>  #define BLK_CLK_EN     0x4
> @@ -498,6 +499,75 @@ static const struct imx8m_blk_ctrl_data imx8mm_disp_blk_ctl_dev_data = {
>         .num_domains = ARRAY_SIZE(imx8mm_disp_blk_ctl_domain_data),
>  };
>
> +
> +static int imx8mn_disp_power_notifier(struct notifier_block *nb,
> +                                     unsigned long action, void *data)
> +{
> +       struct imx8m_blk_ctrl *bc = container_of(nb, struct imx8m_blk_ctrl,
> +                                                power_nb);
> +
> +       if (action != GENPD_NOTIFY_ON && action != GENPD_NOTIFY_PRE_OFF)
> +               return NOTIFY_OK;
> +
> +       /* Enable bus clock and deassert bus reset */
> +       regmap_set_bits(bc->regmap, BLK_CLK_EN, BIT(8));
> +       regmap_set_bits(bc->regmap, BLK_SFT_RSTN, BIT(8));
> +
> +       /*
> +        * On power up we have no software backchannel to the GPC to
> +        * wait for the ADB handshake to happen, so we just delay for a
> +        * bit. On power down the GPC driver waits for the handshake.
> +        */
> +       if (action == GENPD_NOTIFY_ON)
> +               udelay(5);
> +
> +
> +       return NOTIFY_OK;
> +}
> +
> +static const struct imx8m_blk_ctrl_domain_data imx8mn_disp_blk_ctl_domain_data[] = {
> +       [IMX8MN_DISPBLK_PD_MIPI_DSI] = {
> +               .name = "dispblk-mipi-dsi",
> +               .clk_names = (const char *[]){ "dsi-pclk", "dsi-ref", },
> +               .num_clks = 2,
> +               .gpc_name = "mipi-dsi",
> +               .rst_mask = BIT(0) | BIT(1),
> +               .clk_mask = BIT(0) | BIT(1),
> +       },
> +       [IMX8MN_DISPBLK_PD_MIPI_CSI] = {
> +               .name = "dispblk-mipi-csi",
> +               .clk_names = (const char *[]){ "csi-aclk", "csi-pclk" },
> +               .num_clks = 2,
> +               .gpc_name = "mipi-csi",
> +               .rst_mask = BIT(2) | BIT(3),
> +               .clk_mask = BIT(2) | BIT(3),
> +       },
> +       [IMX8MN_DISPBLK_PD_LCDIF] = {
> +               .name = "dispblk-lcdif",
> +               .clk_names = (const char *[]){ "lcdif-axi", "lcdif-apb", "lcdif-pix", },
> +               .num_clks = 3,
> +               .gpc_name = "lcdif",
> +               .rst_mask = BIT(4) | BIT(5),
> +               .clk_mask = BIT(4) | BIT(5),
> +       },
> +       [IMX8MN_DISPBLK_PD_ISI] = {
> +               .name = "dispblk-isi",
> +               .clk_names = (const char *[]){ "disp_axi", "disp_apb", "disp_axi_root",
> +                                               "disp_apb_root"},
> +               .num_clks = 4,
> +               .gpc_name = "isi",
> +               .rst_mask = BIT(6) | BIT(7),
> +               .clk_mask = BIT(6) | BIT(7),
> +       },
> +};
> +
> +static const struct imx8m_blk_ctrl_data imx8mn_disp_blk_ctl_dev_data = {
> +       .max_reg = 0x84,
> +       .power_notifier_fn = imx8mn_disp_power_notifier,
> +       .domains = imx8mn_disp_blk_ctl_domain_data,
> +       .num_domains = ARRAY_SIZE(imx8mn_disp_blk_ctl_domain_data),
> +};
> +
>  static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
>         {
>                 .compatible = "fsl,imx8mm-vpu-blk-ctrl",
> @@ -505,7 +575,10 @@ static const struct of_device_id imx8m_blk_ctrl_of_match[] = {
>         }, {
>                 .compatible = "fsl,imx8mm-disp-blk-ctrl",
>                 .data = &imx8mm_disp_blk_ctl_dev_data
> -       } ,{
> +       }, {
> +               .compatible = "fsl,imx8mn-disp-blk-ctrl",
> +               .data = &imx8mn_disp_blk_ctl_dev_data
> +       }, {
>                 /* Sentinel */
>         }
>  };
> --
> 2.25.1
>

On Sat, Oct 9, 2021 at 11:27 AM Adam Ford <aford173@gmail.com> wrote:
>
> The blk-ctrl and the GPCv2 in the i.MX8MN is similar but slightly different to that
> of the i.MX8MM.  This series is based on work from Lucas Stach for i.MX8MM, but
> adapted for i.MX8MN.  With the additional power domains and blk-ctrl enabled,
> additional peripherals like gpu and USB can be enabled.
>
> V2:  Add mising patches for expanding GPCv2 which are necessary
>        to make the blk-ctl operate.
>      Fix clk names
>      Fix missing references to structures in blk-ctl driver to link
>        them to the device tree.
>

I know Rob had some feedback on the DT bindings updates.  I can
address them in V3, I was hoping to get some feedback from this series
from others who may be interested.

I don't know if it's too late to get this into 5.16 or not, but I'll
submit a V3 this weekend.

adam
> Adam Ford (9):
>   soc: imx: gpcv2: keep i.MX8MN gpumix bus clock enabled
>   soc: imx: gpcv2: Add dispmix and mipi domains to imx8mn
>   dt-bindings: power: imx8mn: add defines for DISP blk-ctrl domains
>   dt-bindings: soc: add binding for i.MX8MN DISP blk-ctrl
>   soc: imx: imx8m-blk-ctrl: add i.MX8MN DISP blk-ctrl
>   arm64: dts: imx8mn: add GPC node
>   arm64: dts: imx8mn: put USB controller into power-domains
>   arm64: dts: imx8mn: add DISP blk-ctrl
>   arm64: dts: imx8mn: Enable GPU
>
>  .../soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml     |  97 +++++++++++++++++
>  arch/arm64/boot/dts/freescale/imx8mn.dtsi     | 103 ++++++++++++++++++
>  drivers/soc/imx/gpcv2.c                       |  26 +++++
>  drivers/soc/imx/imx8m-blk-ctrl.c              |  75 ++++++++++++-
>  include/dt-bindings/power/imx8mn-power.h      |   5 +
>  5 files changed, 305 insertions(+), 1 deletion(-)
>  create mode 100644 Documentation/devicetree/bindings/soc/imx/fsl,imx8mn-disp-blk-ctrl.yaml
>
> --
> 2.25.1
>