| Message ID | YS5u8M97frcjTbJW@arm.com |
|---|---|
| State | New |
| Headers | show
Return-Path: <linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org> X-Original-To: incoming-imx@patchwork.ozlabs.org Delivered-To: patchwork-incoming-imx@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.infradead.org (client-ip=2607:7c80:54:e::133; helo=bombadil.infradead.org; envelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org; receiver=<UNKNOWN>) Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; secure) header.d=lists.infradead.org header.i=@lists.infradead.org header.a=rsa-sha256 header.s=bombadil.20210309 header.b=Zz4YgjcX; dkim-atps=neutral Received: from bombadil.infradead.org (bombadil.infradead.org [IPv6:2607:7c80:54:e::133]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4GzZpP2FDyz9s5R for <incoming-imx@patchwork.ozlabs.org>; Wed, 1 Sep 2021 04:04:45 +1000 (AEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Subject:Cc:To: From:Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=LNUt9BCiirtf1ljIYcuz0cGgNgUS3qqmceYOyJ5I6xg=; b=Zz4YgjcXU/fH0d eKUd/bfXUzWT7oLSHExMikbnLpzSB3msMW93xdwDw2OQhyp0JVvNmsnXzEmJtVEO10KD/yyo8AQNB N8EMPOj2pwNkaP80XGnKoQnXmHhoXjH/+UkHC16fnImHpmxM2eBndrcwukumxaGBhCbDGw0/m8536 nThhNknqyf/Lk4ndZcsLCGy+DYxe/g1A1FtJlupQLzQr/8ZHXkN0fb7shrlEzUZe3sqCCybtbHWKJ +0x2neENFKCLNYvMvTelOlXttUQ/fNwgZXZx46JBKDvMvQUMg22m8S13AU1mm8Ba4qGgCkbaaC63d 6uLAF+GNzPodSZQc0lbw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mL86j-002sIo-EM; Tue, 31 Aug 2021 18:03:37 +0000 Received: from mail.kernel.org ([198.145.29.99]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mL86e-002sHl-Qm for linux-arm-kernel@lists.infradead.org; Tue, 31 Aug 2021 18:03:34 +0000 Received: by mail.kernel.org (Postfix) with ESMTPSA id 5A32160F6C; Tue, 31 Aug 2021 18:03:31 +0000 (UTC) Date: Tue, 31 Aug 2021 19:03:28 +0100 From: Catalin Marinas <catalin.marinas@arm.com> To: Linus Torvalds <torvalds@linux-foundation.org> Cc: Will Deacon <will@kernel.org>, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Zijlstra <peterz@infradead.org>, Ingo Molnar <mingo@kernel.org> Subject: [GIT PULL] arm64 updates for 5.15 Message-ID: <YS5u8M97frcjTbJW@arm.com> MIME-Version: 1.0 Content-Disposition: inline X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210831_110332_958425_8DC776B2 X-CRM114-Status: GOOD ( 20.31 ) X-Spam-Score: -4.8 (----) X-Spam-Report: Spam detection software, running on the system "bombadil.infradead.org", has NOT identified this incoming email as spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see the administrator of that system for details. Content preview: Hi Linus, Please pull the arm64 updates for 5.15 below. The asymmetric AArch32 support patches were queued via tip/sched/arm64 on top of the scheduler counterpart. I merged the tip branch into the arm64 tree (b [...] Content analysis details: (-4.8 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- -5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at https://www.dnswl.org/, high trust [198.145.29.99 listed in list.dnswl.org] -0.0 SPF_PASS SPF: sender matches SPF record 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record 0.2 HEADER_FROM_DIFFERENT_DOMAINS From and EnvelopeFrom 2nd level mail domains are different X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: <linux-arm-kernel.lists.infradead.org> List-Unsubscribe: <http://lists.infradead.org/mailman/options/linux-arm-kernel>, <mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe> List-Archive: <http://lists.infradead.org/pipermail/linux-arm-kernel/> List-Post: <mailto:linux-arm-kernel@lists.infradead.org> List-Help: <mailto:linux-arm-kernel-request@lists.infradead.org?subject=help> List-Subscribe: <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>, <mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" <linux-arm-kernel-bounces@lists.infradead.org> Errors-To: linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org |
| Series |
[GIT,PULL] arm64 updates for 5.15
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The pull request you sent on Tue, 31 Aug 2021 19:03:28 +0100:
> git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-upstream
has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/57c78a234e809e3a0516491e37ae5ccc6eeb21e8
Thank you!
Hi Linus, Please pull the arm64 updates for 5.15 below. The asymmetric AArch32 support patches were queued via tip/sched/arm64 on top of the scheduler counterpart. I merged the tip branch into the arm64 tree (based on -rc3) but since the former was based on -rc6, I had to generate the diffstat manually (dummy merge with upstream and git show --stat). Hopefully it matches yours. Thanks. The following changes since commit 234b8ab6476c5edd5262e2ff563de9498d60044a: sched: Introduce dl_task_check_affinity() to check proposed affinity (2021-08-20 12:33:00 +0200) are available in the Git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux tags/arm64-upstream for you to fetch changes up to 65266a7c6abfa1ad915a362c41bf38576607f1f9: Merge remote-tracking branch 'tip/sched/arm64' into for-next/core (2021-08-31 09:10:00 +0100) ---------------------------------------------------------------- arm64 updates for 5.15: - Support for 32-bit tasks on asymmetric AArch32 systems (on top of the scheduler changes merged via the tip tree). - More entry.S clean-ups and conversion to C. - MTE updates: allow a preferred tag checking mode to be set per CPU (the overhead of synchronous mode is smaller for some CPUs than others); optimisations for kernel entry/exit path; optionally disable MTE on the kernel command line. - Kselftest improvements for SVE and signal handling, PtrAuth. - Fix unlikely race where a TLBI could use stale ASID on an ASID roll-over (found by inspection). - Miscellaneous fixes: disable trapping of PMSNEVFR_EL1 to higher exception levels; drop unnecessary sigdelsetmask() call in the signal32 handling; remove BUG_ON when failing to allocate SVE state (just signal the process); SYM_CODE annotations. - Other trivial clean-ups: use macros instead of magic numbers, remove redundant returns, typos. ---------------------------------------------------------------- Alexandru Elisei (1): arm64: Do not trap PMSNEVFR_EL1 Anshuman Khandual (2): arm64/kexec: Test page size support with new TGRAN range values arm64/perf: Replace '0xf' instances with ID_AA64DFR0_PMUVER_IMP_DEF Catalin Marinas (3): Merge branches 'for-next/mte', 'for-next/misc' and 'for-next/kselftest', remote-tracking branch 'arm64/for-next/perf' into for-next/core Merge branch 'for-next/entry' into for-next/core Merge remote-tracking branch 'tip/sched/arm64' into for-next/core Changbin Du (1): arm64: replace in_irq() with in_hardirq() Jason Wang (3): arm64: use __func__ to get function name in pr_err arm64: unnecessary end 'return;' in void functions arm64: fix typo in a comment Lingyan Huang (1): arm64: SSBS/DIT: print SSBS and DIT bit when printing PSTATE Marc Zyngier (1): arm64: Document the requirement for SCR_EL3.HCE Mark Brown (19): arm64/sme: Document boot requirements for SME kselftest/arm64: Ignore check_gcr_el1_cswitch binary arm64/sve: Make fpsimd_bind_task_to_cpu() static kselftest/arm64: Provide a helper binary and "library" for SVE RDVL kselftest/arm64: Validate vector lengths are set in sve-probe-vls kselftest/arm64: Add tests for SVE vector configuration kselftest/arm64: Add a TODO list for floating point tests arm64: entry: Add SYM_CODE annotation for __bad_stack kselftest/arm64: mte: Fix misleading output when skipping tests kselftest/arm64: pac: Fix skipping of tests on systems without PAC kselftest/arm64: signal: Add SVE to the set of features we can check for kselftest/arm64: signal: Support signal frames with SVE register data kselftest/arm64: signal: Check SVE signal frame shows expected vector length kselftest/arm64: signal: Verify that signals can't change the SVE vector length kselftest/arm64: signal: Add test case for SVE register state in signals kselftest/arm64: signal: Add a TODO list for signal handling tests arm64/sve: Add some comments for sve_save/load_state() arm64/sve: Add a comment documenting the binutils needed for SVE asm arm64/sve: Better handle failure to allocate SVE register storage Mark Rutland (7): arm64: kasan: mte: use a constant kernel GCR_EL1 value arm64: kasan: mte: remove redundant mte_report_once logic arm64: entry: consolidate entry/exit helpers arm64: entry: clarify entry/exit helpers arm64: entry: move bulk of ret_to_user to C arm64: entry: call exit_to_user_mode() from C arm64: head: avoid over-mapping in map_memory Masahiro Yamada (1): arm64: move the (z)install rules to arch/arm64/Makefile Peter Collingbourne (8): arm64: mte: avoid TFSRE0_EL1 related operations unless in async mode arm64: mte: rename gcr_user_excl to mte_ctrl arm64: mte: change ASYNC and SYNC TCF settings into bitfields arm64: move preemption disablement to prctl handlers arm64: mte: introduce a per-CPU tag checking mode preference Documentation: document the preferred tag checking mode feature arm64: mte: optimize GCR_EL1 modification on kernel entry/exit arm64: avoid double ISB on kernel entry Peter Zijlstra (1): Merge branch 'sched/core' Shaokun Zhang (1): arm64: cpufeature: Use defined macro instead of magic numbers Will Deacon (9): arm64: mm: Fix TLBI vs ASID rollover arm64: Implement task_cpu_possible_mask() arm64: exec: Adjust affinity for compat tasks with mismatched 32-bit EL0 arm64: Prevent offlining first CPU with 32-bit EL0 on mismatched system arm64: Advertise CPUs capable of running 32-bit applications in sysfs arm64: Hook up cmdline parameter to allow mismatched 32-bit EL0 arm64: Remove logic to kill 32-bit tasks on 64-bit-only cores Documentation: arm64: describe asymmetric 32-bit support arm64: signal32: Drop pointless call to sigdelsetmask() Xujun Leng (1): arm64: mm: fix comment typo of pud_offset_phys() Yee Lee (1): arm64/cpufeature: Optionally disable MTE via command-line Documentation/ABI/testing/sysfs-devices-system-cpu | 26 + Documentation/admin-guide/kernel-parameters.txt | 14 + Documentation/arm64/asymmetric-32bit.rst | 155 ++++++ Documentation/arm64/booting.rst | 37 +- Documentation/arm64/index.rst | 1 + Documentation/arm64/memory-tagging-extension.rst | 48 +- arch/arm64/Makefile | 7 +- arch/arm64/boot/Makefile | 8 - arch/arm64/include/asm/cpufeature.h | 11 +- arch/arm64/include/asm/el2_setup.h | 13 +- arch/arm64/include/asm/elf.h | 6 +- arch/arm64/include/asm/exception.h | 5 +- arch/arm64/include/asm/fpsimd.h | 1 - arch/arm64/include/asm/fpsimdmacros.h | 1 + arch/arm64/include/asm/kernel-pgtable.h | 4 +- arch/arm64/include/asm/memory.h | 2 - arch/arm64/include/asm/mmu.h | 29 +- arch/arm64/include/asm/mmu_context.h | 13 + arch/arm64/include/asm/mte-kasan.h | 17 - arch/arm64/include/asm/mte.h | 6 - arch/arm64/include/asm/pgtable.h | 2 +- arch/arm64/include/asm/pointer_auth.h | 12 +- arch/arm64/include/asm/processor.h | 10 +- arch/arm64/include/asm/simd.h | 2 +- arch/arm64/include/asm/sysreg.h | 47 +- arch/arm64/include/asm/tlbflush.h | 13 +- arch/arm64/kernel/asm-offsets.c | 2 +- arch/arm64/kernel/cpufeature.c | 58 +- arch/arm64/kernel/entry-common.c | 219 +++++--- arch/arm64/kernel/entry-fpsimd.S | 13 + arch/arm64/kernel/entry.S | 114 ++-- arch/arm64/kernel/fpsimd.c | 14 +- arch/arm64/kernel/head.S | 11 +- arch/arm64/kernel/idreg-override.c | 2 + arch/arm64/kernel/mte.c | 180 ++++--- arch/arm64/kernel/perf_event.c | 2 +- arch/arm64/kernel/pointer_auth.c | 10 +- arch/arm64/kernel/process.c | 78 ++- arch/arm64/kernel/ptrace.c | 5 + arch/arm64/kernel/signal.c | 34 +- arch/arm64/kernel/signal32.c | 6 +- arch/arm64/kernel/suspend.c | 1 - arch/arm64/lib/insn.c | 4 +- arch/arm64/mm/fault.c | 15 +- arch/arm64/mm/proc.S | 3 +- include/linux/kasan-tags.h | 15 + include/uapi/linux/prctl.h | 11 +- lib/test_kasan.c | 2 - mm/kasan/hw_tags.c | 8 - mm/kasan/kasan.h | 22 +- tools/testing/selftests/arm64/fp/.gitignore | 2 + tools/testing/selftests/arm64/fp/Makefile | 11 +- tools/testing/selftests/arm64/fp/TODO | 4 + tools/testing/selftests/arm64/fp/rdvl-sve.c | 14 + tools/testing/selftests/arm64/fp/rdvl.S | 10 + tools/testing/selftests/arm64/fp/rdvl.h | 8 + tools/testing/selftests/arm64/fp/sve-probe-vls.c | 5 + tools/testing/selftests/arm64/fp/vec-syscfg.c | 593 +++++++++++++++++++++ tools/testing/selftests/arm64/mte/.gitignore | 1 + .../testing/selftests/arm64/mte/mte_common_util.c | 2 +- tools/testing/selftests/arm64/pauth/pac.c | 10 +- tools/testing/selftests/arm64/signal/.gitignore | 1 + .../testing/selftests/arm64/signal/test_signals.h | 2 + .../selftests/arm64/signal/test_signals_utils.c | 3 + .../testing/selftests/arm64/signal/testcases/TODO | 2 + .../testcases/fake_sigreturn_sve_change_vl.c | 92 ++++ .../selftests/arm64/signal/testcases/sve_regs.c | 126 +++++ .../selftests/arm64/signal/testcases/sve_vl.c | 68 +++ .../selftests/arm64/signal/testcases/testcases.c | 34 +- 69 files changed, 1843 insertions(+), 464 deletions(-)