| Message ID | a448168cdd6e5aa192c650119490d81aa1d48a19.1627562851.git.wschmidt@linux.ibm.com |
|---|---|
| State | New |
| Headers | show |
| Series | Replace the Power target-specific builtin machinery | expand |
On Thu, 2021-07-29 at 08:30 -0500, Bill Schmidt wrote: > 2021-04-02 Bill Schmidt <wschmidt@linux.ibm.com> > Hi, > gcc/ > * config/rs6000/rs6000-builtin-new.def: Add power7 and power7-64 > stanzas. ok > --- > gcc/config/rs6000/rs6000-builtin-new.def | 39 ++++++++++++++++++++++++ > 1 file changed, 39 insertions(+) > > diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def > index ca694be1ac3..bffce52ee47 100644 > --- a/gcc/config/rs6000/rs6000-builtin-new.def > +++ b/gcc/config/rs6000/rs6000-builtin-new.def > @@ -1957,3 +1957,42 @@ > > const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>); > XXSPLTD_V2DI vsx_xxspltd_v2di {} > + > + > +; Power7 builtins (ISA 2.06). > +[power7] > + const unsigned int __builtin_addg6s (unsigned int, unsigned int); > + ADDG6S addg6s {} Add all of the sixes... (ok). > + > + const signed long __builtin_bpermd (signed long, signed long); > + BPERMD bpermd_di {} > + > + const unsigned int __builtin_cbcdtd (unsigned int); > + CBCDTD cbcdtd {} > + > + const unsigned int __builtin_cdtbcd (unsigned int); > + CDTBCD cdtbcd {} > + > + const signed int __builtin_divwe (signed int, signed int); > + DIVWE dive_si {} > + > + const unsigned int __builtin_divweu (unsigned int, unsigned int); > + DIVWEU diveu_si {} > + > + const vsq __builtin_pack_vector_int128 (unsigned long long, unsigned long long); > + PACK_V1TI packv1ti {} > + > + void __builtin_ppc_speculation_barrier (); > + SPECBARR speculation_barrier {} > + > + const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>); > + UNPACK_V1TI unpackv1ti {} > + > + > +; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing). > +[power7-64] > + const signed long long __builtin_divde (signed long long, signed long long); > + DIVDE dive_di {} > + > + const unsigned long long __builtin_divdeu (unsigned long long, unsigned long long); > + DIVDEU diveu_di {} ok thanks -Will
On Tue, Aug 10, 2021 at 11:16:41AM -0500, will schmidt wrote: > On Thu, 2021-07-29 at 08:30 -0500, Bill Schmidt wrote: > > + const unsigned int __builtin_addg6s (unsigned int, unsigned int); > > + ADDG6S addg6s {} > > Add all of the sixes... (ok). "Add and generate sixes." Look it up in the ISA if you aren't confused enough yet :-) Segher
diff --git a/gcc/config/rs6000/rs6000-builtin-new.def b/gcc/config/rs6000/rs6000-builtin-new.def index ca694be1ac3..bffce52ee47 100644 --- a/gcc/config/rs6000/rs6000-builtin-new.def +++ b/gcc/config/rs6000/rs6000-builtin-new.def @@ -1957,3 +1957,42 @@ const vsll __builtin_vsx_xxspltd_2di (vsll, const int<1>); XXSPLTD_V2DI vsx_xxspltd_v2di {} + + +; Power7 builtins (ISA 2.06). +[power7] + const unsigned int __builtin_addg6s (unsigned int, unsigned int); + ADDG6S addg6s {} + + const signed long __builtin_bpermd (signed long, signed long); + BPERMD bpermd_di {} + + const unsigned int __builtin_cbcdtd (unsigned int); + CBCDTD cbcdtd {} + + const unsigned int __builtin_cdtbcd (unsigned int); + CDTBCD cdtbcd {} + + const signed int __builtin_divwe (signed int, signed int); + DIVWE dive_si {} + + const unsigned int __builtin_divweu (unsigned int, unsigned int); + DIVWEU diveu_si {} + + const vsq __builtin_pack_vector_int128 (unsigned long long, unsigned long long); + PACK_V1TI packv1ti {} + + void __builtin_ppc_speculation_barrier (); + SPECBARR speculation_barrier {} + + const unsigned long __builtin_unpack_vector_int128 (vsq, const int<1>); + UNPACK_V1TI unpackv1ti {} + + +; Power7 builtins requiring 64-bit GPRs (even with 32-bit addressing). +[power7-64] + const signed long long __builtin_divde (signed long long, signed long long); + DIVDE dive_di {} + + const unsigned long long __builtin_divdeu (unsigned long long, unsigned long long); + DIVDEU diveu_di {}