| Message ID | 20210721192650.499597025@linutronix.de |
|---|---|
| State | New |
| Headers | show |
| Series | PCI/MSI, x86: Cure a couple of inconsistencies | expand |
On Wed, Jul 21, 2021 at 09:11:30PM +0200, Thomas Gleixner wrote: > Nothing enforces the posted writes to be visible when the function > returns. Flush them even if the flush might be redundant when the entry is > masked already as the unmask will flush as well. This is either setup or a > rare affinity change event so the extra flush is not the end of the world. > > While this is more a theoretical issue especially the X86 MSI affinity > stter mechanism relies on the assumption that the update has reached the stter? > hardware when the function returns. > > Again, as this never has been enfocred the Fixes tag refers to a commit in: s/enfocred/enforced/ > git://git.kernel.org/pub/scm/linux/kernel/git/tglx/history.git
On Thu, 22 Jul 2021 22:54:48 +0100, Andy Shevchenko <andy.shevchenko@gmail.com> wrote: > > [1 <text/plain; UTF-8 (7bit)>] > On Friday, July 23, 2021, Bjorn Helgaas <helgaas@kernel.org> wrote: > > > On Wed, Jul 21, 2021 at 09:11:30PM +0200, Thomas Gleixner wrote: > > > Nothing enforces the posted writes to be visible when the function > > > returns. Flush them even if the flush might be redundant when the entry > > is > > > masked already as the unmask will flush as well. This is either setup or > > a > > > rare affinity change event so the extra flush is not the end of the > > world. > > > > > > While this is more a theoretical issue especially the X86 MSI affinity > > > stter mechanism relies on the assumption that the update has reached the > > > > stter? > > > Setter I suppose My bet is on 'steer', given that this is about affinity management. M.
--- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -311,6 +311,9 @@ void __pci_write_msi_msg(struct msi_desc if (unmasked) __pci_msix_desc_mask_irq(entry, 0); + + /* Ensure that the writes are visible in the device */ + readl(base + PCI_MSIX_ENTRY_DATA); } else { int pos = dev->msi_cap; u16 msgctl; @@ -331,6 +334,8 @@ void __pci_write_msi_msg(struct msi_desc pci_write_config_word(dev, pos + PCI_MSI_DATA_32, msg->data); } + /* Ensure that the writes are visible in the device */ + pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl); } skip:
Nothing enforces the posted writes to be visible when the function returns. Flush them even if the flush might be redundant when the entry is masked already as the unmask will flush as well. This is either setup or a rare affinity change event so the extra flush is not the end of the world. While this is more a theoretical issue especially the X86 MSI affinity stter mechanism relies on the assumption that the update has reached the hardware when the function returns. Again, as this never has been enfocred the Fixes tag refers to a commit in: git://git.kernel.org/pub/scm/linux/kernel/git/tglx/history.git Fixes: f036d4ea5fa7 ("[PATCH] ia32 Message Signalled Interrupt support") Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Bjorn Helgaas <bhelgaas@google.com> Cc: linux-pci@vger.kernel.org --- drivers/pci/msi.c | 5 +++++ 1 file changed, 5 insertions(+)