Message ID | 92711c73eb79a6c0bf69b3b86dff9a8575fab081.camel@mengyan1223.wang |
---|---|
State | New |
Headers | show |
Series | mips: check MSA support for vector modes [PR100760,PR100761,PR100762] | expand |
Ping patch: https://gcc.gnu.org/pipermail/gcc-patches/2021-June/573213.html Status update: bootstrapped with BOOT_CFLAGS="-O3 -mmsa -mloongson-mmi" (it failed without the patch), and regtested on mips64el-linux-gnu with no new regression. On Sat, 2021-06-19 at 15:34 +0800, Xi Ruoyao wrote: > Check if the vector mode is really supported by MSA in certain cases, > instead of testing ISA_HAS_MSA. Simply testing ISA_HAS_MSA can cause > ICE when MSA is enabled besides other MIPS SIMD extensions (notably, > Loongson MMI). > > Bootstrapped and tested on mips64el-linux-gnu. OK to commit? > > gcc/ > > * config/mips/mips.c (mips_const_insns): Use > MSA_SUPPORTED_MODE_P > instead of ISA_HAS_MSA. > (mips_expand_vec_unpack): Likewise. > (mips_expand_vector_init): Likewise. > > gcc/testsuite/ > > * testsuite/gcc.target/mips/pr100760.c: New test. > * testsuite/gcc.target/mips/pr100761.c: New test. > * testsuite/gcc.target/mips/pr100762.c: New test.
Looks good to me, but I have no right to approve. On Wed, Jun 30, 2021 at 9:17 PM Xi Ruoyao <xry111@mengyan1223.wang> wrote: > > Ping patch: > https://gcc.gnu.org/pipermail/gcc-patches/2021-June/573213.html > > Status update: bootstrapped with BOOT_CFLAGS="-O3 -mmsa -mloongson-mmi" > (it failed without the patch), and regtested on mips64el-linux-gnu with > no new regression. > > On Sat, 2021-06-19 at 15:34 +0800, Xi Ruoyao wrote: > > Check if the vector mode is really supported by MSA in certain cases, > > instead of testing ISA_HAS_MSA. Simply testing ISA_HAS_MSA can cause > > ICE when MSA is enabled besides other MIPS SIMD extensions (notably, > > Loongson MMI). > > > > Bootstrapped and tested on mips64el-linux-gnu. OK to commit? > > > > gcc/ > > > > * config/mips/mips.c (mips_const_insns): Use > > MSA_SUPPORTED_MODE_P > > instead of ISA_HAS_MSA. > > (mips_expand_vec_unpack): Likewise. > > (mips_expand_vector_init): Likewise. > > > > gcc/testsuite/ > > > > * testsuite/gcc.target/mips/pr100760.c: New test. > > * testsuite/gcc.target/mips/pr100761.c: New test. > > * testsuite/gcc.target/mips/pr100762.c: New test. > -- > Xi Ruoyao <xry111@mengyan1223.wang> >
On 7/5/2021 8:04 PM, Paul Hua wrote:
> Looks good to me, but I have no right to approve.
But your opinions are well respected :-)
I'll go ahead and ACK, though in general I'm stepping away from
reviewing target specific work.
jeff
On Thu, 2021-07-08 at 17:20 -0600, Jeff Law wrote: > > On 7/5/2021 8:04 PM, Paul Hua wrote: > > Looks good to me, but I have no right to approve. > But your opinions are well respected :-) > > I'll go ahead and ACK, though in general I'm stepping away from > reviewing target specific work. Thanks Paul & Jeff! I'll edit the ChangeLog a little (PRnnnn is now required in ChangeLog) and commit it then.
On Fri, 2021-07-09 at 14:01 +0800, Xi Ruoyao wrote: > On Thu, 2021-07-08 at 17:20 -0600, Jeff Law wrote: > > > > On 7/5/2021 8:04 PM, Paul Hua wrote: > > > Looks good to me, but I have no right to approve. > > But your opinions are well respected :-) > > > > I'll go ahead and ACK, though in general I'm stepping away from > > reviewing target specific work. > > Thanks Paul & Jeff! > > I'll edit the ChangeLog a little (PRnnnn is now required in ChangeLog) > and commit it then. Pushed @ 82625a42.
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 1f1475cf400..00a8eef96aa 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -2879,7 +2879,7 @@ mips_const_insns (rtx x) return mips_build_integer (codes, INTVAL (x)); case CONST_VECTOR: - if (ISA_HAS_MSA + if (MSA_SUPPORTED_MODE_P (GET_MODE (x)) && mips_const_vector_same_int_p (x, GET_MODE (x), -512, 511)) return 1; /* Fall through. */ @@ -21732,7 +21732,7 @@ mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p) rtx (*cmpFunc) (rtx, rtx, rtx); rtx tmp, dest, zero; - if (ISA_HAS_MSA) + if (MSA_SUPPORTED_MODE_P (imode)) { switch (imode) { @@ -21994,7 +21994,7 @@ mips_expand_vector_init (rtx target, rtx vals) all_same = false; } - if (ISA_HAS_MSA) + if (MSA_SUPPORTED_MODE_P (vmode)) { if (all_same) { diff --git a/gcc/testsuite/gcc.target/mips/pr100760.c b/gcc/testsuite/gcc.target/mips/pr100760.c new file mode 100644 index 00000000000..d715b85e790 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/pr100760.c @@ -0,0 +1,10 @@ +/* PR target/100760 + This was triggering an ICE with "maximum number of generated reload + insns per insn achieved (90)" when compiled with -mmsa -mloongson-mmi. */ + +/* { dg-do compile } */ +/* { dg-options "-mmsa -mloongson-mmi" } */ + +typedef __INT32_TYPE__ int32_t; +typedef int32_t a __attribute__((__vector_size__(8))); +void b() { a x = (a){1, 1}; } diff --git a/gcc/testsuite/gcc.target/mips/pr100761.c b/gcc/testsuite/gcc.target/mips/pr100761.c new file mode 100644 index 00000000000..cc2598ee023 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/pr100761.c @@ -0,0 +1,17 @@ +/* PR target/100761 + This was triggering an ICE in mips_expand_vec_unpack when compiled with + -mmsa -mloongson-mmi. */ + +/* { dg-do compile } */ +/* { dg-options "-mmsa -mloongson-mmi" } */ + +typedef __INT8_TYPE__ int8_t; +typedef __INT16_TYPE__ int16_t; +typedef int8_t i8x8 __attribute__((__vector_size__(8))); +typedef int16_t i16x8 __attribute__((__vector_size__(16))); + +i8x8 a; + +void f() { + i16x8 b = __builtin_convertvector (a, i16x8); +} diff --git a/gcc/testsuite/gcc.target/mips/pr100762.c b/gcc/testsuite/gcc.target/mips/pr100762.c new file mode 100644 index 00000000000..89c1185317c --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/pr100762.c @@ -0,0 +1,25 @@ +/* PR target/100762 + This was triggering an ICE in mips_expand_vector_init when compiled with + -mmsa -mloongson-mmi. */ + +/* { dg-do compile } */ +/* { dg-options "-mmsa -mloongson-mmi" } */ + +typedef __INT32_TYPE__ int32_t; +typedef int32_t i32x2 __attribute__((__vector_size__(8))); + +i32x2 cmp(i32x2 a, i32x2 b) { + return a >= b; +} + +i32x2 shift(i32x2 a, i32x2 b) { + return a >> b; +} + +i32x2 mul(i32x2 a, i32x2 b) { + return a * b; +} + +i32x2 div(i32x2 a, i32x2 b) { + return a / b; +}