| Message ID | 20210325192643.2190069-1-robert.hancock@calian.com |
|---|---|
| Headers | show |
| Series | Si5341 driver updates | expand |
On Thu, 2021-03-25 at 13:26 -0600, Robert Hancock wrote: > Various fixes and enhancements to the Si5341 driver. > > Changed since v2: > -changed regulator reference for output supply from vdd to vddo to match > data sheet > > Changed since v1: > -wait up to 300ms for DEVICE_READY > -use regmap_read_poll_timeout rather than fixed wait when waiting for PLL > lock and input presence > -make si5341_remove static > > Robert Hancock (9): > dt-bindings: clock: clk-si5341: Add new attributes > clk: si5341: Wait for DEVICE_READY on startup > clk: si5341: Avoid divide errors due to bogus register contents > clk: si5341: Check for input clock presence and PLL lock on startup > clk: si5341: Update initialization magic > clk: si5341: Allow different output VDD_SEL values > clk: si5341: Add silabs,xaxb-ext-clk property > clk: si5341: Add silabs,iovdd-33 property > clk: si5341: Add sysfs properties to allow checking/resetting device > faults > > .../bindings/clock/silabs,si5341.txt | 16 +- > drivers/clk/clk-si5341.c | 324 ++++++++++++++++-- > 2 files changed, 304 insertions(+), 36 deletions(-) > Ping.. any feedback on this patch set? (Aside from one ack on patch 1..)
Quoting Robert Hancock (2021-03-25 12:26:36) > The Si5341 datasheet warns that before accessing any other registers, > including the PAGE register, we need to wait for the DEVICE_READY register > to indicate the device is ready, or the process of the device loading its > state from NVM can be corrupted. Wait for DEVICE_READY on startup before > continuing initialization. This is done using a raw I2C register read > prior to setting up regmap to avoid any potential unwanted automatic PAGE > register accesses from regmap at this stage. > > Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver") > Signed-off-by: Robert Hancock <robert.hancock@calian.com> > --- Applied to clk-next
Quoting Robert Hancock (2021-03-25 12:26:37) > If the Si5341 is being initially programmed and has no stored NVM > configuration, some of the register contents may contain unexpected > values, such as zeros, which could cause divide by zero errors during > driver initialization. Trap errors caused by zero registers or zero clock > rates which could result in divide errors later in the code. > > Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver") > Signed-off-by: Robert Hancock <robert.hancock@calian.com> > --- Applied to clk-next
Quoting Robert Hancock (2021-03-25 12:26:38) > After initializing the device, wait for it to report that the input > clock is present and the PLL has locked before declaring success. > > Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver") > Signed-off-by: Robert Hancock <robert.hancock@calian.com> > --- Applied to clk-next
Quoting Robert Hancock (2021-03-25 12:26:39) > Update the default register settings to include the VCO_RESET_CALCODE > settings (set by the SiLabs ClockBuilder software but not described in > the datasheet). Also update part of the initialization sequence to match > ClockBuilder and the datasheet. > > Fixes: 3044a860fd ("clk: Add Si5341/Si5340 driver") > Signed-off-by: Robert Hancock <robert.hancock@calian.com> > --- Applied to clk-next
Quoting Robert Hancock (2021-03-25 12:26:40) > The driver was not previously programming the VDD_SEL values for each > output to indicate what external VDDO voltage was used for each. Add > ability to specify a regulator supplying the VDDO pin for each output of > the device. The voltage of the regulator is used to automatically set the > VDD_SEL value appropriately. If no regulator is specified and the chip is > being reconfigured, assume 2.5V which appears to be the chip default. > > Signed-off-by: Robert Hancock <robert.hancock@calian.com> > --- Applied to clk-next
Quoting Robert Hancock (2021-03-25 12:26:41) > Add a property to allow specifying that the device XA/XB pins are used for > an external clock input rather than for a clock crystal. > > Signed-off-by: Robert Hancock <robert.hancock@calian.com> > --- Applied to clk-next
Quoting Robert Hancock (2021-03-25 12:26:42) > Add a property to allow specifying that the external I2C IO pins are using > 3.3V voltage thresholds rather than 1.8V. > > Signed-off-by: Robert Hancock <robert.hancock@calian.com> > --- Applied to clk-next
Quoting Robert Hancock (2021-03-25 12:26:43) > Add sysfs property files to allow viewing the current and latched states of > the input present and PLL lock bits, and allow resetting the latched fault > state. This allows manual checks or automated userspace polling for faults > occurring after initialization. > > Signed-off-by: Robert Hancock <robert.hancock@calian.com> > --- Applied to clk-next
Various fixes and enhancements to the Si5341 driver. Changed since v2: -changed regulator reference for output supply from vdd to vddo to match data sheet Changed since v1: -wait up to 300ms for DEVICE_READY -use regmap_read_poll_timeout rather than fixed wait when waiting for PLL lock and input presence -make si5341_remove static Robert Hancock (9): dt-bindings: clock: clk-si5341: Add new attributes clk: si5341: Wait for DEVICE_READY on startup clk: si5341: Avoid divide errors due to bogus register contents clk: si5341: Check for input clock presence and PLL lock on startup clk: si5341: Update initialization magic clk: si5341: Allow different output VDD_SEL values clk: si5341: Add silabs,xaxb-ext-clk property clk: si5341: Add silabs,iovdd-33 property clk: si5341: Add sysfs properties to allow checking/resetting device faults .../bindings/clock/silabs,si5341.txt | 16 +- drivers/clk/clk-si5341.c | 324 ++++++++++++++++-- 2 files changed, 304 insertions(+), 36 deletions(-)