| Message ID | 20210510172442.11146-6-vigneshr@ti.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Lokesh Vutla |
| Headers | show |
| Series | J72xx: R5 SPL DMA support post HSM Rearch | expand |
On 10/05/21 10:54 pm, Vignesh Raghavendra wrote: > R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING > CFG, TCHAN CFG and RCHAN CFG address ranges. > > Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> > --- > arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++++++++++ > .../k3-j7200-common-proc-board-u-boot.dtsi | 26 +++++++++++++++++++ > .../k3-j721e-common-proc-board-u-boot.dtsi | 14 ++++++++++ If these are specific to R5, then it should be moved to R5 dts no? -u-boot.dtsi will be applied to A53 dts as well. Thanks and regards, Lokesh > 3 files changed, 54 insertions(+) > > diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi > index b0602d1dad..2840258518 100644 > --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi > +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi > @@ -35,11 +35,25 @@ > u-boot,dm-spl; > > ringacc@2b800000 { > + reg = <0x0 0x2b800000 0x0 0x400000>, > + <0x0 0x2b000000 0x0 0x400000>, > + <0x0 0x28590000 0x0 0x100>, > + <0x0 0x2a500000 0x0 0x40000>, > + <0x0 0x28440000 0x0 0x40000>; > + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; > u-boot,dm-spl; > ti,dma-ring-reset-quirk; > }; > > dma-controller@285c0000 { > + reg = <0x0 0x285c0000 0x0 0x100>, > + <0x0 0x284c0000 0x0 0x4000>, > + <0x0 0x2a800000 0x0 0x40000>, > + <0x0 0x284a0000 0x0 0x4000>, > + <0x0 0x2aa00000 0x0 0x40000>, > + <0x0 0x28400000 0x0 0x2000>; > + reg-names = "gcfg", "rchan", "rchanrt", "tchan", > + "tchanrt", "rflow"; > u-boot,dm-spl; > }; > }; > diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi > index c3aae65b39..41ce9fcb59 100644 > --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi > +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi > @@ -40,6 +40,32 @@ > chipid@43000014 { > u-boot,dm-spl; > }; > + > + mcu-navss{ > + u-boot,dm-spl; > + > + ringacc@2b800000 { > + reg = <0x0 0x2b800000 0x0 0x400000>, > + <0x0 0x2b000000 0x0 0x400000>, > + <0x0 0x28590000 0x0 0x100>, > + <0x0 0x2a500000 0x0 0x40000>, > + <0x0 0x28440000 0x0 0x40000>; > + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; > + u-boot,dm-spl; > + }; > + > + dma-controller@285c0000 { > + reg = <0x0 0x285c0000 0x0 0x100>, > + <0x0 0x284c0000 0x0 0x4000>, > + <0x0 0x2a800000 0x0 0x40000>, > + <0x0 0x284a0000 0x0 0x4000>, > + <0x0 0x2aa00000 0x0 0x40000>, > + <0x0 0x28400000 0x0 0x2000>; > + reg-names = "gcfg", "rchan", "rchanrt", "tchan", > + "tchanrt", "rflow"; > + u-boot,dm-spl; > + }; > + }; > }; > > &secure_proxy_main { > diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi > index 1135de5a92..ed64f2720d 100644 > --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi > +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi > @@ -54,10 +54,24 @@ > u-boot,dm-spl; > > ringacc@2b800000 { > + reg = <0x0 0x2b800000 0x0 0x400000>, > + <0x0 0x2b000000 0x0 0x400000>, > + <0x0 0x28590000 0x0 0x100>, > + <0x0 0x2a500000 0x0 0x40000>, > + <0x0 0x28440000 0x0 0x40000>; > + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; > u-boot,dm-spl; > }; > > dma-controller@285c0000 { > + reg = <0x0 0x285c0000 0x0 0x100>, > + <0x0 0x284c0000 0x0 0x4000>, > + <0x0 0x2a800000 0x0 0x40000>, > + <0x0 0x284a0000 0x0 0x4000>, > + <0x0 0x2aa00000 0x0 0x40000>, > + <0x0 0x28400000 0x0 0x2000>; > + reg-names = "gcfg", "rchan", "rchanrt", "tchan", > + "tchanrt", "rflow"; > u-boot,dm-spl; > }; > }; >
On 5/11/21 10:21 AM, Lokesh Vutla wrote: > > > On 10/05/21 10:54 pm, Vignesh Raghavendra wrote: >> R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING >> CFG, TCHAN CFG and RCHAN CFG address ranges. >> >> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> >> --- >> arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++++++++++ >> .../k3-j7200-common-proc-board-u-boot.dtsi | 26 +++++++++++++++++++ >> .../k3-j721e-common-proc-board-u-boot.dtsi | 14 ++++++++++ > > If these are specific to R5, then it should be moved to R5 dts no? -u-boot.dtsi > will be applied to A53 dts as well. > Not really.. There registers are present within respective IPs. A53/A72 use DM APIs to configure these registers whereas R5 does direct programming. I intend to add these ranges to kernel DT as well. Until then, will be in -u-boot.dtsi. > Thanks and regards, > Lokesh > >> 3 files changed, 54 insertions(+) >> >> diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi >> index b0602d1dad..2840258518 100644 >> --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi >> +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi >> @@ -35,11 +35,25 @@ >> u-boot,dm-spl; >> >> ringacc@2b800000 { >> + reg = <0x0 0x2b800000 0x0 0x400000>, >> + <0x0 0x2b000000 0x0 0x400000>, >> + <0x0 0x28590000 0x0 0x100>, >> + <0x0 0x2a500000 0x0 0x40000>, >> + <0x0 0x28440000 0x0 0x40000>; >> + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; >> u-boot,dm-spl; >> ti,dma-ring-reset-quirk; >> }; >> >> dma-controller@285c0000 { >> + reg = <0x0 0x285c0000 0x0 0x100>, >> + <0x0 0x284c0000 0x0 0x4000>, >> + <0x0 0x2a800000 0x0 0x40000>, >> + <0x0 0x284a0000 0x0 0x4000>, >> + <0x0 0x2aa00000 0x0 0x40000>, >> + <0x0 0x28400000 0x0 0x2000>; >> + reg-names = "gcfg", "rchan", "rchanrt", "tchan", >> + "tchanrt", "rflow"; >> u-boot,dm-spl; >> }; >> }; >> diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi >> index c3aae65b39..41ce9fcb59 100644 >> --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi >> +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi >> @@ -40,6 +40,32 @@ >> chipid@43000014 { >> u-boot,dm-spl; >> }; >> + >> + mcu-navss{ >> + u-boot,dm-spl; >> + >> + ringacc@2b800000 { >> + reg = <0x0 0x2b800000 0x0 0x400000>, >> + <0x0 0x2b000000 0x0 0x400000>, >> + <0x0 0x28590000 0x0 0x100>, >> + <0x0 0x2a500000 0x0 0x40000>, >> + <0x0 0x28440000 0x0 0x40000>; >> + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; >> + u-boot,dm-spl; >> + }; >> + >> + dma-controller@285c0000 { >> + reg = <0x0 0x285c0000 0x0 0x100>, >> + <0x0 0x284c0000 0x0 0x4000>, >> + <0x0 0x2a800000 0x0 0x40000>, >> + <0x0 0x284a0000 0x0 0x4000>, >> + <0x0 0x2aa00000 0x0 0x40000>, >> + <0x0 0x28400000 0x0 0x2000>; >> + reg-names = "gcfg", "rchan", "rchanrt", "tchan", >> + "tchanrt", "rflow"; >> + u-boot,dm-spl; >> + }; >> + }; >> }; >> >> &secure_proxy_main { >> diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi >> index 1135de5a92..ed64f2720d 100644 >> --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi >> +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi >> @@ -54,10 +54,24 @@ >> u-boot,dm-spl; >> >> ringacc@2b800000 { >> + reg = <0x0 0x2b800000 0x0 0x400000>, >> + <0x0 0x2b000000 0x0 0x400000>, >> + <0x0 0x28590000 0x0 0x100>, >> + <0x0 0x2a500000 0x0 0x40000>, >> + <0x0 0x28440000 0x0 0x40000>; >> + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; >> u-boot,dm-spl; >> }; >> >> dma-controller@285c0000 { >> + reg = <0x0 0x285c0000 0x0 0x100>, >> + <0x0 0x284c0000 0x0 0x4000>, >> + <0x0 0x2a800000 0x0 0x40000>, >> + <0x0 0x284a0000 0x0 0x4000>, >> + <0x0 0x2aa00000 0x0 0x40000>, >> + <0x0 0x28400000 0x0 0x2000>; >> + reg-names = "gcfg", "rchan", "rchanrt", "tchan", >> + "tchanrt", "rflow"; >> u-boot,dm-spl; >> }; >> }; >>
On 11/05/21 11:34 am, Vignesh Raghavendra wrote: > > > On 5/11/21 10:21 AM, Lokesh Vutla wrote: >> >> >> On 10/05/21 10:54 pm, Vignesh Raghavendra wrote: >>> R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING >>> CFG, TCHAN CFG and RCHAN CFG address ranges. >>> >>> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> >>> --- >>> arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++++++++++ >>> .../k3-j7200-common-proc-board-u-boot.dtsi | 26 +++++++++++++++++++ >>> .../k3-j721e-common-proc-board-u-boot.dtsi | 14 ++++++++++ >> >> If these are specific to R5, then it should be moved to R5 dts no? -u-boot.dtsi >> will be applied to A53 dts as well. >> > > Not really.. There registers are present within respective IPs. A53/A72 > use DM APIs to configure these registers whereas R5 does direct > programming. I intend to add these ranges to kernel DT as well. Until > then, will be in -u-boot.dtsi. > You intend to add mcu-navss ringacc to kernel dts as well. I am fine with this. But please remember to update u-boot dts once you update kernel dts Thanks and regards, Lokesh >> Thanks and regards, >> Lokesh >> >>> 3 files changed, 54 insertions(+) >>> >>> diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi >>> index b0602d1dad..2840258518 100644 >>> --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi >>> +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi >>> @@ -35,11 +35,25 @@ >>> u-boot,dm-spl; >>> >>> ringacc@2b800000 { >>> + reg = <0x0 0x2b800000 0x0 0x400000>, >>> + <0x0 0x2b000000 0x0 0x400000>, >>> + <0x0 0x28590000 0x0 0x100>, >>> + <0x0 0x2a500000 0x0 0x40000>, >>> + <0x0 0x28440000 0x0 0x40000>; >>> + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; >>> u-boot,dm-spl; >>> ti,dma-ring-reset-quirk; >>> }; >>> >>> dma-controller@285c0000 { >>> + reg = <0x0 0x285c0000 0x0 0x100>, >>> + <0x0 0x284c0000 0x0 0x4000>, >>> + <0x0 0x2a800000 0x0 0x40000>, >>> + <0x0 0x284a0000 0x0 0x4000>, >>> + <0x0 0x2aa00000 0x0 0x40000>, >>> + <0x0 0x28400000 0x0 0x2000>; >>> + reg-names = "gcfg", "rchan", "rchanrt", "tchan", >>> + "tchanrt", "rflow"; >>> u-boot,dm-spl; >>> }; >>> }; >>> diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi >>> index c3aae65b39..41ce9fcb59 100644 >>> --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi >>> +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi >>> @@ -40,6 +40,32 @@ >>> chipid@43000014 { >>> u-boot,dm-spl; >>> }; >>> + >>> + mcu-navss{ >>> + u-boot,dm-spl; >>> + >>> + ringacc@2b800000 { >>> + reg = <0x0 0x2b800000 0x0 0x400000>, >>> + <0x0 0x2b000000 0x0 0x400000>, >>> + <0x0 0x28590000 0x0 0x100>, >>> + <0x0 0x2a500000 0x0 0x40000>, >>> + <0x0 0x28440000 0x0 0x40000>; >>> + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; >>> + u-boot,dm-spl; >>> + }; >>> + >>> + dma-controller@285c0000 { >>> + reg = <0x0 0x285c0000 0x0 0x100>, >>> + <0x0 0x284c0000 0x0 0x4000>, >>> + <0x0 0x2a800000 0x0 0x40000>, >>> + <0x0 0x284a0000 0x0 0x4000>, >>> + <0x0 0x2aa00000 0x0 0x40000>, >>> + <0x0 0x28400000 0x0 0x2000>; >>> + reg-names = "gcfg", "rchan", "rchanrt", "tchan", >>> + "tchanrt", "rflow"; >>> + u-boot,dm-spl; >>> + }; >>> + }; >>> }; >>> >>> &secure_proxy_main { >>> diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi >>> index 1135de5a92..ed64f2720d 100644 >>> --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi >>> +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi >>> @@ -54,10 +54,24 @@ >>> u-boot,dm-spl; >>> >>> ringacc@2b800000 { >>> + reg = <0x0 0x2b800000 0x0 0x400000>, >>> + <0x0 0x2b000000 0x0 0x400000>, >>> + <0x0 0x28590000 0x0 0x100>, >>> + <0x0 0x2a500000 0x0 0x40000>, >>> + <0x0 0x28440000 0x0 0x40000>; >>> + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; >>> u-boot,dm-spl; >>> }; >>> >>> dma-controller@285c0000 { >>> + reg = <0x0 0x285c0000 0x0 0x100>, >>> + <0x0 0x284c0000 0x0 0x4000>, >>> + <0x0 0x2a800000 0x0 0x40000>, >>> + <0x0 0x284a0000 0x0 0x4000>, >>> + <0x0 0x2aa00000 0x0 0x40000>, >>> + <0x0 0x28400000 0x0 0x2000>; >>> + reg-names = "gcfg", "rchan", "rchanrt", "tchan", >>> + "tchanrt", "rflow"; >>> u-boot,dm-spl; >>> }; >>> }; >>>
On 5/12/21 11:40 AM, Lokesh Vutla wrote: > > > On 11/05/21 11:34 am, Vignesh Raghavendra wrote: >> >> >> On 5/11/21 10:21 AM, Lokesh Vutla wrote: >>> >>> >>> On 10/05/21 10:54 pm, Vignesh Raghavendra wrote: >>>> R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING >>>> CFG, TCHAN CFG and RCHAN CFG address ranges. >>>> >>>> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> >>>> --- >>>> arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++++++++++ >>>> .../k3-j7200-common-proc-board-u-boot.dtsi | 26 +++++++++++++++++++ >>>> .../k3-j721e-common-proc-board-u-boot.dtsi | 14 ++++++++++ >>> >>> If these are specific to R5, then it should be moved to R5 dts no? -u-boot.dtsi >>> will be applied to A53 dts as well. >>> >> >> Not really.. There registers are present within respective IPs. A53/A72 >> use DM APIs to configure these registers whereas R5 does direct >> programming. I intend to add these ranges to kernel DT as well. Until >> then, will be in -u-boot.dtsi. >> > > You intend to add mcu-navss ringacc to kernel dts as well. I am fine with this. MCU RINGACC node itself is present in kernel dts, its just cfg register ranges that are not populated. > But please remember to update u-boot dts once you update kernel dts > Sure will do... Regards Vignesh > Thanks and regards, > Lokesh > >>> Thanks and regards, >>> Lokesh >>> >>>> 3 files changed, 54 insertions(+) >>>> >>>> diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi >>>> index b0602d1dad..2840258518 100644 >>>> --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi >>>> +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi >>>> @@ -35,11 +35,25 @@ >>>> u-boot,dm-spl; >>>> >>>> ringacc@2b800000 { >>>> + reg = <0x0 0x2b800000 0x0 0x400000>, >>>> + <0x0 0x2b000000 0x0 0x400000>, >>>> + <0x0 0x28590000 0x0 0x100>, >>>> + <0x0 0x2a500000 0x0 0x40000>, >>>> + <0x0 0x28440000 0x0 0x40000>; >>>> + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; >>>> u-boot,dm-spl; >>>> ti,dma-ring-reset-quirk; >>>> }; >>>> >>>> dma-controller@285c0000 { >>>> + reg = <0x0 0x285c0000 0x0 0x100>, >>>> + <0x0 0x284c0000 0x0 0x4000>, >>>> + <0x0 0x2a800000 0x0 0x40000>, >>>> + <0x0 0x284a0000 0x0 0x4000>, >>>> + <0x0 0x2aa00000 0x0 0x40000>, >>>> + <0x0 0x28400000 0x0 0x2000>; >>>> + reg-names = "gcfg", "rchan", "rchanrt", "tchan", >>>> + "tchanrt", "rflow"; >>>> u-boot,dm-spl; >>>> }; >>>> }; >>>> diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi >>>> index c3aae65b39..41ce9fcb59 100644 >>>> --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi >>>> +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi >>>> @@ -40,6 +40,32 @@ >>>> chipid@43000014 { >>>> u-boot,dm-spl; >>>> }; >>>> + >>>> + mcu-navss{ >>>> + u-boot,dm-spl; >>>> + >>>> + ringacc@2b800000 { >>>> + reg = <0x0 0x2b800000 0x0 0x400000>, >>>> + <0x0 0x2b000000 0x0 0x400000>, >>>> + <0x0 0x28590000 0x0 0x100>, >>>> + <0x0 0x2a500000 0x0 0x40000>, >>>> + <0x0 0x28440000 0x0 0x40000>; >>>> + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; >>>> + u-boot,dm-spl; >>>> + }; >>>> + >>>> + dma-controller@285c0000 { >>>> + reg = <0x0 0x285c0000 0x0 0x100>, >>>> + <0x0 0x284c0000 0x0 0x4000>, >>>> + <0x0 0x2a800000 0x0 0x40000>, >>>> + <0x0 0x284a0000 0x0 0x4000>, >>>> + <0x0 0x2aa00000 0x0 0x40000>, >>>> + <0x0 0x28400000 0x0 0x2000>; >>>> + reg-names = "gcfg", "rchan", "rchanrt", "tchan", >>>> + "tchanrt", "rflow"; >>>> + u-boot,dm-spl; >>>> + }; >>>> + }; >>>> }; >>>> >>>> &secure_proxy_main { >>>> diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi >>>> index 1135de5a92..ed64f2720d 100644 >>>> --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi >>>> +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi >>>> @@ -54,10 +54,24 @@ >>>> u-boot,dm-spl; >>>> >>>> ringacc@2b800000 { >>>> + reg = <0x0 0x2b800000 0x0 0x400000>, >>>> + <0x0 0x2b000000 0x0 0x400000>, >>>> + <0x0 0x28590000 0x0 0x100>, >>>> + <0x0 0x2a500000 0x0 0x40000>, >>>> + <0x0 0x28440000 0x0 0x40000>; >>>> + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; >>>> u-boot,dm-spl; >>>> }; >>>> >>>> dma-controller@285c0000 { >>>> + reg = <0x0 0x285c0000 0x0 0x100>, >>>> + <0x0 0x284c0000 0x0 0x4000>, >>>> + <0x0 0x2a800000 0x0 0x40000>, >>>> + <0x0 0x284a0000 0x0 0x4000>, >>>> + <0x0 0x2aa00000 0x0 0x40000>, >>>> + <0x0 0x28400000 0x0 0x2000>; >>>> + reg-names = "gcfg", "rchan", "rchanrt", "tchan", >>>> + "tchanrt", "rflow"; >>>> u-boot,dm-spl; >>>> }; >>>> }; >>>>
On 12/05/21 11:50 am, Vignesh Raghavendra wrote: > > > On 5/12/21 11:40 AM, Lokesh Vutla wrote: >> >> >> On 11/05/21 11:34 am, Vignesh Raghavendra wrote: >>> >>> >>> On 5/11/21 10:21 AM, Lokesh Vutla wrote: >>>> >>>> >>>> On 10/05/21 10:54 pm, Vignesh Raghavendra wrote: >>>>> R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING >>>>> CFG, TCHAN CFG and RCHAN CFG address ranges. >>>>> >>>>> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> >>>>> --- >>>>> arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++++++++++ >>>>> .../k3-j7200-common-proc-board-u-boot.dtsi | 26 +++++++++++++++++++ >>>>> .../k3-j721e-common-proc-board-u-boot.dtsi | 14 ++++++++++ >>>> >>>> If these are specific to R5, then it should be moved to R5 dts no? -u-boot.dtsi >>>> will be applied to A53 dts as well. >>>> >>> >>> Not really.. There registers are present within respective IPs. A53/A72 >>> use DM APIs to configure these registers whereas R5 does direct >>> programming. I intend to add these ranges to kernel DT as well. Until >>> then, will be in -u-boot.dtsi. >>> >> >> You intend to add mcu-navss ringacc to kernel dts as well. I am fine with this. > > MCU RINGACC node itself is present in kernel dts, its just cfg register > ranges that are not populated. okay, please mention this intention in commit description. It says needed only for R5 but code is in u-boot.dtsi with the intention of being added in kernel dts. It is confusing. Thanks and regards, Lokesh
diff --git a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi index b0602d1dad..2840258518 100644 --- a/arch/arm/dts/k3-am654-base-board-u-boot.dtsi +++ b/arch/arm/dts/k3-am654-base-board-u-boot.dtsi @@ -35,11 +35,25 @@ u-boot,dm-spl; ringacc@2b800000 { + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; u-boot,dm-spl; ti,dma-ring-reset-quirk; }; dma-controller@285c0000 { + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x284c0000 0x0 0x4000>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x284a0000 0x0 0x4000>, + <0x0 0x2aa00000 0x0 0x40000>, + <0x0 0x28400000 0x0 0x2000>; + reg-names = "gcfg", "rchan", "rchanrt", "tchan", + "tchanrt", "rflow"; u-boot,dm-spl; }; }; diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi index c3aae65b39..41ce9fcb59 100644 --- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi @@ -40,6 +40,32 @@ chipid@43000014 { u-boot,dm-spl; }; + + mcu-navss{ + u-boot,dm-spl; + + ringacc@2b800000 { + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; + u-boot,dm-spl; + }; + + dma-controller@285c0000 { + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x284c0000 0x0 0x4000>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x284a0000 0x0 0x4000>, + <0x0 0x2aa00000 0x0 0x40000>, + <0x0 0x28400000 0x0 0x2000>; + reg-names = "gcfg", "rchan", "rchanrt", "tchan", + "tchanrt", "rflow"; + u-boot,dm-spl; + }; + }; }; &secure_proxy_main { diff --git a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi index 1135de5a92..ed64f2720d 100644 --- a/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi +++ b/arch/arm/dts/k3-j721e-common-proc-board-u-boot.dtsi @@ -54,10 +54,24 @@ u-boot,dm-spl; ringacc@2b800000 { + reg = <0x0 0x2b800000 0x0 0x400000>, + <0x0 0x2b000000 0x0 0x400000>, + <0x0 0x28590000 0x0 0x100>, + <0x0 0x2a500000 0x0 0x40000>, + <0x0 0x28440000 0x0 0x40000>; + reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg"; u-boot,dm-spl; }; dma-controller@285c0000 { + reg = <0x0 0x285c0000 0x0 0x100>, + <0x0 0x284c0000 0x0 0x4000>, + <0x0 0x2a800000 0x0 0x40000>, + <0x0 0x284a0000 0x0 0x4000>, + <0x0 0x2aa00000 0x0 0x40000>, + <0x0 0x28400000 0x0 0x2000>; + reg-names = "gcfg", "rchan", "rchanrt", "tchan", + "tchanrt", "rflow"; u-boot,dm-spl; }; };
R5 SPL needs access to cfg space of Rings and UDMAP, therefore add RING CFG, TCHAN CFG and RCHAN CFG address ranges. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> --- arch/arm/dts/k3-am654-base-board-u-boot.dtsi | 14 ++++++++++ .../k3-j7200-common-proc-board-u-boot.dtsi | 26 +++++++++++++++++++ .../k3-j721e-common-proc-board-u-boot.dtsi | 14 ++++++++++ 3 files changed, 54 insertions(+)