Message ID | 20210415084518.120625-3-green.wan@sifive.com |
---|---|
State | Superseded |
Delegated to: | Andes |
Headers | show |
Series | arch: riscv: cpu: Add callback to init each core | expand |
> From: Green Wan [mailto:green.wan@sifive.com] > Sent: Thursday, April 15, 2021 4:45 PM > Cc: Green Wan; Sean Anderson; Bin Meng; Rick Jian-Zhi Chen(陳建志); Bin Meng; Simon Glass; Pragnesh Patel; Jagan Teki; Atish Patra; Leo Yu-Chi Liang(梁育齊); u-boot@lists.denx.de > Subject: [RFC PATCH v6 2/2] arch: riscv: cpu: fu740: clear feature disable CSR > nitpicky: arch > Clear feature disable CSR to turn on all features of hart. The detail > is specified at section, 'SiFive Feature Disable CSR', in user manual > > https://sifive.cdn.prismic.io/sifive/aee0dd4c-d156-496e-a6c4-db0cf54bbe68_sifive_U74MC_rtl_full_20G1.03.00_manual.pdf > > Signed-off-by: Green Wan <green.wan@sifive.com> > Reviewed-by: Sean Anderson <seanga2@gmail.com> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > --- > arch/riscv/cpu/fu740/spl.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) Reviewed-by: Rick Chen <rick@andestech.com>
diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c index ea0b2283a2..55e30346ff 100644 --- a/arch/riscv/cpu/fu740/spl.c +++ b/arch/riscv/cpu/fu740/spl.c @@ -6,6 +6,9 @@ #include <dm.h> #include <log.h> +#include <asm/csr.h> + +#define CSR_U74_FEATURE_DISABLE 0x7c1 int spl_soc_init(void) { @@ -21,3 +24,15 @@ int spl_soc_init(void) return 0; } + +void harts_early_init(void) +{ + /* + * Feature Disable CSR + * + * Clear feature disable CSR to '0' to turn on all features for + * each core. This operation must be in M-mode. + */ + if (CONFIG_IS_ENABLED(RISCV_MMODE)) + csr_write(CSR_U74_FEATURE_DISABLE, 0); +}