[v6,09/48] powerpc/64s: remove KVM SKIP test from instruction breakpoint handler

The code being executed in KVM_GUEST_MODE_SKIP is hypervisor code with
MSR[IR]=0, so the faults of concern are the d-side ones caused by access
to guest context by the hypervisor.

Instruction breakpoint interrupts are not a concern here. It's unlikely
any good would come of causing breaks in this code, but skipping the
instruction that caused it won't help matters (e.g., skip the mtmsr that
sets MSR[DR]=0 or clears KVM_GUEST_MODE_SKIP).

 [Paul notes: the 0x1300 interrupt was dropped from the architecture a
  long time ago and is not generated by P7, P8, P9 or P10.]

In fact it does not exist in ISA v2.01, which is the earliest supported
now, but did exist in 600 series designs (some of the earliest 64-bit
powerpcs), so it could probably be removed entirely.

Acked-by: Paul Mackerras <paulus@ozlabs.org>
Reviewed-by: Daniel Axtens <dja@axtens.net>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 arch/powerpc/kernel/exceptions-64s.S | 1 -
 1 file changed, 1 deletion(-)

Excerpts from Nicholas Piggin's message of April 5, 2021 11:19 am:
> The code being executed in KVM_GUEST_MODE_SKIP is hypervisor code with
> MSR[IR]=0, so the faults of concern are the d-side ones caused by access
> to guest context by the hypervisor.
> 
> Instruction breakpoint interrupts are not a concern here. It's unlikely
> any good would come of causing breaks in this code, but skipping the
> instruction that caused it won't help matters (e.g., skip the mtmsr that
> sets MSR[DR]=0 or clears KVM_GUEST_MODE_SKIP).
> 
>  [Paul notes: the 0x1300 interrupt was dropped from the architecture a
>   long time ago and is not generated by P7, P8, P9 or P10.]
> 
> In fact it does not exist in ISA v2.01, which is the earliest supported
> now, but did exist in 600 series designs (some of the earliest 64-bit
> powerpcs), so it could probably be removed entirely.

Hmm, I looked at a 970 manual and that does have a 0x1300, but 2.01 
(which it implements) does not, if I'm reading correctly. Seems strange
the interrupt would be taken out of the architecture then implemented,
but not mine to wonder why. Maybe I misread something.

We support G5 in Linux but not HV KVM, maybe PR KVM is supported though?

At any rate it can't be removed from Linux 64s yet, and may be relevant
for PR KVM, but that should still be okay according this reasoning they
should not be applicable to SKIP interrupts.

Thanks,
Nick

> 
> Acked-by: Paul Mackerras <paulus@ozlabs.org>
> Reviewed-by: Daniel Axtens <dja@axtens.net>
> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
>  arch/powerpc/kernel/exceptions-64s.S | 1 -
>  1 file changed, 1 deletion(-)
> 
> diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
> index a0515cb829c2..c9c446ccff54 100644
> --- a/arch/powerpc/kernel/exceptions-64s.S
> +++ b/arch/powerpc/kernel/exceptions-64s.S
> @@ -2553,7 +2553,6 @@ EXC_VIRT_NONE(0x5200, 0x100)
>  INT_DEFINE_BEGIN(instruction_breakpoint)
>  	IVEC=0x1300
>  #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
> -	IKVM_SKIP=1
>  	IKVM_REAL=1
>  #endif
>  INT_DEFINE_END(instruction_breakpoint)
> -- 
> 2.23.0
> 
>

On Tue, Apr 06, 2021 at 12:44:45PM +1000, Nicholas Piggin wrote:
> Excerpts from Nicholas Piggin's message of April 5, 2021 11:19 am:
> > The code being executed in KVM_GUEST_MODE_SKIP is hypervisor code with
> > MSR[IR]=0, so the faults of concern are the d-side ones caused by access
> > to guest context by the hypervisor.
> > 
> > Instruction breakpoint interrupts are not a concern here. It's unlikely
> > any good would come of causing breaks in this code, but skipping the
> > instruction that caused it won't help matters (e.g., skip the mtmsr that
> > sets MSR[DR]=0 or clears KVM_GUEST_MODE_SKIP).
> > 
> >  [Paul notes: the 0x1300 interrupt was dropped from the architecture a
> >   long time ago and is not generated by P7, P8, P9 or P10.]
> > 
> > In fact it does not exist in ISA v2.01, which is the earliest supported
> > now, but did exist in 600 series designs (some of the earliest 64-bit
> > powerpcs), so it could probably be removed entirely.
> 
> Hmm, I looked at a 970 manual and that does have a 0x1300, but 2.01 
> (which it implements) does not, if I'm reading correctly. Seems strange
> the interrupt would be taken out of the architecture then implemented,
> but not mine to wonder why. Maybe I misread something.

It was probably put in at Apple's request, since they had been using
IABR and the 0x1300 interrupt on the 6xx/7xx/7xxx CPUs.

Paul.