| Message ID | 20210316090236.2018-1-rsalvaterra@gmail.com |
|---|---|
| State | Superseded |
| Headers | show |
| Series | ramips/mt7621: drop two obsolete patches | expand |
On Tue, 16 Mar 2021 at 09:02, Rui Salvaterra <rsalvaterra@gmail.com> wrote: > > Although the title is trivial, the potential impact of these changes is enough > in itself to warrant more extensive justification, which follows: > > 202-weak_reordering.patch - In order to fix random hangs on MT7621, we've been > selecting WEAK_REORDERING_BEYOND_LLSC for years [1]. However, these random hangs > have been most likely caused by an oversight in the MIPS implementation of the > kernel memory consistency model, which has already been fixed for some time (and > stable-backported) [2]. > > 321-mt7621-timer.patch - We've also been carrying this patch for many years [3], > in order to fix a timer calibration issue on MT7621. Turns out, after retesting > with a recent kernel (5.10), the system works perfectly fine without it (no > rcu_sched stalls or inconsistent BogoMIPS values across CPUs). > > The GENERIC_CLOCKEVENTS_BROADCAST selection, however, is an unrelated change, > should be kept (although we're not building with cpuidle support), and is thus > moved to a new patch, 202-generic-clockevents-broadcast.patch. This change also > requires a manual refresh of both 322-mt7621-fix-cpu-clk-add-clkdev.patch and > 323-mt7621-memory-detect.patch. > > [1] https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=5c971cd6fdd7298a2017bdb6bea870088eddb8b9 > [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/mips?h=linux-5.4.y&id=42344113ba7a1ed7b5654cd5270af0d5698d8521 > [3] https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=6f4a903533361a2906a4d94ac6f597cd9c6c47bc > > Suggested-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> > Tested-by: Donald Hoskins <grommish@gmail.com> > Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com> [patch snipped] Ping. Any comments on this? I'm thinking of splitting it in two patches to make reviewing easier, adding the cpuidle patch as the last one and resend as a series of three. Thoughts? Thanks in advance, Rui
On Tue, Mar 30, 2021 at 2:43 AM Rui Salvaterra <rsalvaterra@gmail.com> wrote: > > On Tue, 16 Mar 2021 at 09:02, Rui Salvaterra <rsalvaterra@gmail.com> wrote: > > > > Although the title is trivial, the potential impact of these changes is enough > > in itself to warrant more extensive justification, which follows: > > > > 202-weak_reordering.patch - In order to fix random hangs on MT7621, we've been > > selecting WEAK_REORDERING_BEYOND_LLSC for years [1]. However, these random hangs > > have been most likely caused by an oversight in the MIPS implementation of the > > kernel memory consistency model, which has already been fixed for some time (and > > stable-backported) [2]. > > > > 321-mt7621-timer.patch - We've also been carrying this patch for many years [3], > > in order to fix a timer calibration issue on MT7621. Turns out, after retesting > > with a recent kernel (5.10), the system works perfectly fine without it (no > > rcu_sched stalls or inconsistent BogoMIPS values across CPUs). > > > > The GENERIC_CLOCKEVENTS_BROADCAST selection, however, is an unrelated change, > > should be kept (although we're not building with cpuidle support), and is thus > > moved to a new patch, 202-generic-clockevents-broadcast.patch. This change also > > requires a manual refresh of both 322-mt7621-fix-cpu-clk-add-clkdev.patch and > > 323-mt7621-memory-detect.patch. > > > > [1] https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=5c971cd6fdd7298a2017bdb6bea870088eddb8b9 > > [2] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/mips?h=linux-5.4.y&id=42344113ba7a1ed7b5654cd5270af0d5698d8521 > > [3] https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=6f4a903533361a2906a4d94ac6f597cd9c6c47bc > > > > Suggested-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> > > Tested-by: Donald Hoskins <grommish@gmail.com> > > Signed-off-by: Rui Salvaterra <rsalvaterra@gmail.com> > > [patch snipped] > > Ping. Any comments on this? I'm thinking of splitting it in two > patches to make reviewing easier, adding the cpuidle patch as the last > one and resend as a series of three. Thoughts? My opinion is go ahead and supersede the series with your proposed updates, since no maintainer appears to have spent any time on this yet. Ilya
On Tue, 30 Mar 2021 at 19:27, Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com> wrote: > > My opinion is go ahead and supersede the series with your proposed > updates, since no maintainer appears to have spent any time on this > yet. That as my reasoning too. Will respin, thanks!
diff --git a/target/linux/ramips/patches-5.10/202-weak_reordering.patch b/target/linux/ramips/patches-5.10/202-generic-clockevents-broadcast.patch similarity index 82% rename from target/linux/ramips/patches-5.10/202-weak_reordering.patch rename to target/linux/ramips/patches-5.10/202-generic-clockevents-broadcast.patch index 074e16642f..8661c8a3d0 100644 --- a/target/linux/ramips/patches-5.10/202-weak_reordering.patch +++ b/target/linux/ramips/patches-5.10/202-generic-clockevents-broadcast.patch @@ -4,7 +4,7 @@ select CLKSRC_MIPS_GIC select HAVE_PCI if PCI_MT7621 select SOC_BUS -+ select WEAK_REORDERING_BEYOND_LLSC ++ select GENERIC_CLOCKEVENTS_BROADCAST endchoice choice diff --git a/target/linux/ramips/patches-5.10/321-mt7621-timer.patch b/target/linux/ramips/patches-5.10/321-mt7621-timer.patch deleted file mode 100644 index 91e14ad63b..0000000000 --- a/target/linux/ramips/patches-5.10/321-mt7621-timer.patch +++ /dev/null @@ -1,87 +0,0 @@ ---- a/arch/mips/ralink/mt7621.c -+++ b/arch/mips/ralink/mt7621.c -@@ -9,6 +9,7 @@ - #include <linux/init.h> - #include <linux/slab.h> - #include <linux/sys_soc.h> -+#include <linux/jiffies.h> - - #include <asm/mipsregs.h> - #include <asm/smp-ops.h> -@@ -16,6 +17,7 @@ - #include <asm/mach-ralink/ralink_regs.h> - #include <asm/mach-ralink/mt7621.h> - #include <asm/mips-boards/launch.h> -+#include <asm/delay.h> - - #include <pinmux.h> - -@@ -161,6 +163,58 @@ bool plat_cpu_core_present(int core) - return true; - } - -+#define LPS_PREC 8 -+/* -+* Re-calibration lpj(loop-per-jiffy). -+* (derived from kernel/calibrate.c) -+*/ -+static int udelay_recal(void) -+{ -+ unsigned int i, lpj = 0; -+ unsigned long ticks, loopbit; -+ int lps_precision = LPS_PREC; -+ -+ lpj = (1<<12); -+ -+ while ((lpj <<= 1) != 0) { -+ /* wait for "start of" clock tick */ -+ ticks = jiffies; -+ while (ticks == jiffies) -+ /* nothing */; -+ -+ /* Go .. */ -+ ticks = jiffies; -+ __delay(lpj); -+ ticks = jiffies - ticks; -+ if (ticks) -+ break; -+ } -+ -+ /* -+ * Do a binary approximation to get lpj set to -+ * equal one clock (up to lps_precision bits) -+ */ -+ lpj >>= 1; -+ loopbit = lpj; -+ while (lps_precision-- && (loopbit >>= 1)) { -+ lpj |= loopbit; -+ ticks = jiffies; -+ while (ticks == jiffies) -+ /* nothing */; -+ ticks = jiffies; -+ __delay(lpj); -+ if (jiffies != ticks) /* longer than 1 tick */ -+ lpj &= ~loopbit; -+ } -+ printk(KERN_INFO "%d CPUs re-calibrate udelay(lpj = %d)\n", NR_CPUS, lpj); -+ -+ for(i=0; i< NR_CPUS; i++) -+ cpu_data[i].udelay_val = lpj; -+ -+ return 0; -+} -+device_initcall(udelay_recal); -+ - void prom_soc_init(struct ralink_soc_info *soc_info) - { - void __iomem *sysc = (void __iomem *) KSEG1ADDR(MT7621_SYSC_BASE); ---- a/arch/mips/ralink/Kconfig -+++ b/arch/mips/ralink/Kconfig -@@ -63,6 +63,7 @@ choice - select HAVE_PCI if PCI_MT7621 - select SOC_BUS - select WEAK_REORDERING_BEYOND_LLSC -+ select GENERIC_CLOCKEVENTS_BROADCAST - endchoice - - choice diff --git a/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch b/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch index 723c628790..be5fee54b2 100644 --- a/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch +++ b/target/linux/ramips/patches-5.10/322-mt7621-fix-cpu-clk-add-clkdev.patch @@ -36,10 +36,10 @@ #define MT7621_DDR2_SIZE_MAX 256 --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c -@@ -10,6 +10,10 @@ +@@ -9,6 +9,10 @@ + #include <linux/init.h> #include <linux/slab.h> #include <linux/sys_soc.h> - #include <linux/jiffies.h> +#include <linux/clk.h> +#include <linux/clkdev.h> +#include <linux/clk-provider.h> @@ -47,15 +47,15 @@ #include <asm/mipsregs.h> #include <asm/smp-ops.h> -@@ -18,6 +22,7 @@ +@@ -16,6 +20,7 @@ + #include <asm/mach-ralink/ralink_regs.h> #include <asm/mach-ralink/mt7621.h> #include <asm/mips-boards/launch.h> - #include <asm/delay.h> +#include <asm/time.h> #include <pinmux.h> -@@ -108,11 +113,89 @@ static struct rt2880_pmx_group mt7621_pi +@@ -106,11 +111,89 @@ static struct rt2880_pmx_group mt7621_pi { 0 } }; diff --git a/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch b/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch index 07c7588661..9f80d02638 100644 --- a/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch +++ b/target/linux/ramips/patches-5.10/323-mt7621-memory-detect.patch @@ -44,10 +44,10 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com> #define MT7621_CHIP_NAME1 0x20203132 --- a/arch/mips/ralink/mt7621.c +++ b/arch/mips/ralink/mt7621.c -@@ -10,11 +10,13 @@ +@@ -9,11 +9,13 @@ + #include <linux/init.h> #include <linux/slab.h> #include <linux/sys_soc.h> - #include <linux/jiffies.h> +#include <linux/memblock.h> #include <linux/clk.h> #include <linux/clkdev.h> @@ -58,7 +58,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com> #include <asm/mipsregs.h> #include <asm/smp-ops.h> #include <asm/mips-cps.h> -@@ -57,6 +59,8 @@ +@@ -55,6 +57,8 @@ #define MT7621_GPIO_MODE_SDHCI_SHIFT 18 #define MT7621_GPIO_MODE_SDHCI_GPIO 1 @@ -67,7 +67,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com> static struct rt2880_pmx_func uart1_grp[] = { FUNC("uart1", 0, 1, 2) }; static struct rt2880_pmx_func i2c_grp[] = { FUNC("i2c", 0, 3, 2) }; static struct rt2880_pmx_func uart3_grp[] = { -@@ -141,6 +145,26 @@ static struct clk *__init mt7621_add_sys +@@ -139,6 +143,26 @@ static struct clk *__init mt7621_add_sys return clk; } @@ -94,7 +94,7 @@ Signed-off-by: Chuanhong Guo <gch981213@gmail.com> void __init ralink_clk_init(void) { u32 syscfg, xtal_sel, clkcfg, clk_sel, curclk, ffiv, ffrac; -@@ -346,10 +370,7 @@ void prom_soc_init(struct ralink_soc_inf +@@ -292,10 +316,7 @@ void prom_soc_init(struct ralink_soc_inf (rev >> CHIP_REV_VER_SHIFT) & CHIP_REV_VER_MASK, (rev & CHIP_REV_ECO_MASK));