| Message ID | 20210318082046.51546-1-benjamin.gaignard@collabora.com |
|---|---|
| Headers | show |
| Series | Add HANTRO G2/HEVC decoder support for IMX8MQ | expand |
On Thu, Mar 18, 2021 at 09:20:36AM +0100, Benjamin Gaignard wrote: > In order to be able to share the control hardware block between > VPUs use a syscon instead a ioremap it in the driver. > To keep the compatibility with older DT if 'nxp,imx8mq-vpu-ctrl' > phandle is not found look at 'ctrl' reg-name. > With the method it becomes useless to provide a list of register > names so remove it. > > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> > --- > version 5: > - use syscon instead of VPU reset driver. > - if DT doesn't provide syscon keep backward compatibilty by using > 'ctrl' reg-name. > > drivers/staging/media/hantro/hantro.h | 5 +- > drivers/staging/media/hantro/imx8m_vpu_hw.c | 52 ++++++++++++--------- > 2 files changed, 34 insertions(+), 23 deletions(-) > > diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h > index 65f9f7ea7dcf..a99a96b84b5e 100644 > --- a/drivers/staging/media/hantro/hantro.h > +++ b/drivers/staging/media/hantro/hantro.h > @@ -13,6 +13,7 @@ > #define HANTRO_H_ > > #include <linux/platform_device.h> > +#include <linux/regmap.h> > #include <linux/videodev2.h> > #include <linux/wait.h> > #include <linux/clk.h> > @@ -167,7 +168,7 @@ hantro_vdev_to_func(struct video_device *vdev) > * @reg_bases: Mapped addresses of VPU registers. > * @enc_base: Mapped address of VPU encoder register for convenience. > * @dec_base: Mapped address of VPU decoder register for convenience. > - * @ctrl_base: Mapped address of VPU control block. > + * @ctrl_base: Regmap of VPU control block. > * @vpu_mutex: Mutex to synchronize V4L2 calls. > * @irqlock: Spinlock to synchronize access to data structures > * shared with interrupt handlers. > @@ -186,7 +187,7 @@ struct hantro_dev { > void __iomem **reg_bases; > void __iomem *enc_base; > void __iomem *dec_base; > - void __iomem *ctrl_base; > + struct regmap *ctrl_base; > > struct mutex vpu_mutex; /* video_device lock */ > spinlock_t irqlock; > diff --git a/drivers/staging/media/hantro/imx8m_vpu_hw.c b/drivers/staging/media/hantro/imx8m_vpu_hw.c > index c222de075ef4..bd9d135dd440 100644 > --- a/drivers/staging/media/hantro/imx8m_vpu_hw.c > +++ b/drivers/staging/media/hantro/imx8m_vpu_hw.c > @@ -7,6 +7,7 @@ > > #include <linux/clk.h> > #include <linux/delay.h> > +#include <linux/mfd/syscon.h> > > #include "hantro.h" > #include "hantro_jpeg.h" > @@ -24,30 +25,28 @@ > #define CTRL_G1_PP_FUSE 0x0c > #define CTRL_G2_DEC_FUSE 0x10 > > +static const struct regmap_config ctrl_regmap_ctrl = { > + .reg_bits = 32, > + .val_bits = 32, > + .reg_stride = 0x14, > +}; > + > static void imx8m_soft_reset(struct hantro_dev *vpu, u32 reset_bits) > { > - u32 val; > - > /* Assert */ > - val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); > - val &= ~reset_bits; > - writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); > + regmap_update_bits(vpu->ctrl_base, CTRL_SOFT_RESET, reset_bits, 0); > > udelay(2); > > /* Release */ > - val = readl(vpu->ctrl_base + CTRL_SOFT_RESET); > - val |= reset_bits; > - writel(val, vpu->ctrl_base + CTRL_SOFT_RESET); > + regmap_update_bits(vpu->ctrl_base, CTRL_SOFT_RESET, > + reset_bits, reset_bits); > } > > static void imx8m_clk_enable(struct hantro_dev *vpu, u32 clock_bits) > { > - u32 val; > - > - val = readl(vpu->ctrl_base + CTRL_CLOCK_ENABLE); > - val |= clock_bits; > - writel(val, vpu->ctrl_base + CTRL_CLOCK_ENABLE); > + regmap_update_bits(vpu->ctrl_base, CTRL_CLOCK_ENABLE, > + clock_bits, clock_bits); > } > > static int imx8mq_runtime_resume(struct hantro_dev *vpu) > @@ -64,9 +63,9 @@ static int imx8mq_runtime_resume(struct hantro_dev *vpu) > imx8m_clk_enable(vpu, CLOCK_G1 | CLOCK_G2); > > /* Set values of the fuse registers */ > - writel(0xffffffff, vpu->ctrl_base + CTRL_G1_DEC_FUSE); > - writel(0xffffffff, vpu->ctrl_base + CTRL_G1_PP_FUSE); > - writel(0xffffffff, vpu->ctrl_base + CTRL_G2_DEC_FUSE); > + regmap_write(vpu->ctrl_base, CTRL_G1_DEC_FUSE, 0xffffffff); > + regmap_write(vpu->ctrl_base, CTRL_G1_PP_FUSE, 0xffffffff); > + regmap_write(vpu->ctrl_base, CTRL_G2_DEC_FUSE, 0xffffffff); > > clk_bulk_disable_unprepare(vpu->variant->num_clocks, vpu->clocks); > > @@ -150,8 +149,22 @@ static irqreturn_t imx8m_vpu_g1_irq(int irq, void *dev_id) > > static int imx8mq_vpu_hw_init(struct hantro_dev *vpu) > { > - vpu->dec_base = vpu->reg_bases[0]; > - vpu->ctrl_base = vpu->reg_bases[vpu->variant->num_regs - 1]; > + struct device_node *np = vpu->dev->of_node; > + > + vpu->ctrl_base = syscon_regmap_lookup_by_phandle(np, "nxp,imx8mq-vpu-ctrl"); I think calling this nxp,imx8m-vpu-ctrl would allow to share this with i.MX8MM later. Otherwise, Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> thanks Philipp
On Thu, Mar 18, 2021 at 09:20:45AM +0100, Benjamin Gaignard wrote: > Add variant to IMX8M to enable G2/HEVC codec. > Define the capabilities for the hardware up to 3840x2160. > G2 doesn't have postprocessor, use the same clocks and got it > own interruption. > > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> regards Philipp
On Thu, Mar 18, 2021 at 09:20:46AM +0100, Benjamin Gaignard wrote: > Split VPU node in two: one for G1 and one for G2 since they are > different hardware blocks. > Add syscon for hardware control block. > Remove reg-names property that is useless. > Each VPU node only need one interrupt. > > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> > --- > version 5: > - use syscon instead of VPU reset > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 43 ++++++++++++++++++----- > 1 file changed, 34 insertions(+), 9 deletions(-) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 17c449e12c2e..b537d153ebbd 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -1329,15 +1329,16 @@ usb3_phy1: usb-phy@382f0040 { > status = "disabled"; > }; > > - vpu: video-codec@38300000 { > + vpu_ctrl: syscon@38320000 { > + compatible = "nxp,imx8mq-vpu-ctrl", "syscon"; > + reg = <0x38320000 0x10000>; > + }; > + > + vpu_g1: video-codec@38300000 { > compatible = "nxp,imx8mq-vpu"; > - reg = <0x38300000 0x10000>, > - <0x38310000 0x10000>, > - <0x38320000 0x10000>; > - reg-names = "g1", "g2", "ctrl"; > - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "g1", "g2"; > + reg = <0x38300000 0x10000>; > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "g1"; > clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > <&clk IMX8MQ_CLK_VPU_G2_ROOT>, > <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > @@ -1350,9 +1351,33 @@ vpu: video-codec@38300000 { > <&clk IMX8MQ_VPU_PLL_OUT>, > <&clk IMX8MQ_SYS1_PLL_800M>, > <&clk IMX8MQ_VPU_PLL>; > - assigned-clock-rates = <600000000>, <600000000>, > + assigned-clock-rates = <600000000>, <300000000>, I'd like to see this mentioned in the commit message. > + <800000000>, <0>; > + power-domains = <&pgc_vpu>; > + nxp,imx8mq-vpu-ctrl = <&vpu_ctrl>; > + }; > + > + vpu_g2: video-codec@38310000 { > + compatible = "nxp,imx8mq-vpu-g2"; > + reg = <0x38310000 0x10000>; > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "g2"; > + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>, > + <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > + clock-names = "g1", "g2", "bus"; > + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, Can the G1 clock configuration be dropped from the G2 device node and the G2 clock configuration from the G1 device node? It looks weird that these devices configure each other's clocks. regards Philipp
Le 26/03/2021 à 15:24, Philipp Zabel a écrit : > On Thu, Mar 18, 2021 at 09:20:46AM +0100, Benjamin Gaignard wrote: >> Split VPU node in two: one for G1 and one for G2 since they are >> different hardware blocks. >> Add syscon for hardware control block. >> Remove reg-names property that is useless. >> Each VPU node only need one interrupt. >> >> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> >> --- >> version 5: >> - use syscon instead of VPU reset >> >> arch/arm64/boot/dts/freescale/imx8mq.dtsi | 43 ++++++++++++++++++----- >> 1 file changed, 34 insertions(+), 9 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi >> index 17c449e12c2e..b537d153ebbd 100644 >> --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi >> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi >> @@ -1329,15 +1329,16 @@ usb3_phy1: usb-phy@382f0040 { >> status = "disabled"; >> }; >> >> - vpu: video-codec@38300000 { >> + vpu_ctrl: syscon@38320000 { >> + compatible = "nxp,imx8mq-vpu-ctrl", "syscon"; >> + reg = <0x38320000 0x10000>; >> + }; >> + >> + vpu_g1: video-codec@38300000 { >> compatible = "nxp,imx8mq-vpu"; >> - reg = <0x38300000 0x10000>, >> - <0x38310000 0x10000>, >> - <0x38320000 0x10000>; >> - reg-names = "g1", "g2", "ctrl"; >> - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, >> - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; >> - interrupt-names = "g1", "g2"; >> + reg = <0x38300000 0x10000>; >> + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "g1"; >> clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, >> <&clk IMX8MQ_CLK_VPU_G2_ROOT>, >> <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; >> @@ -1350,9 +1351,33 @@ vpu: video-codec@38300000 { >> <&clk IMX8MQ_VPU_PLL_OUT>, >> <&clk IMX8MQ_SYS1_PLL_800M>, >> <&clk IMX8MQ_VPU_PLL>; >> - assigned-clock-rates = <600000000>, <600000000>, >> + assigned-clock-rates = <600000000>, <300000000>, > I'd like to see this mentioned in the commit message. Yes I would do that. The value comes from the datasheet. > >> + <800000000>, <0>; >> + power-domains = <&pgc_vpu>; >> + nxp,imx8mq-vpu-ctrl = <&vpu_ctrl>; >> + }; >> + >> + vpu_g2: video-codec@38310000 { >> + compatible = "nxp,imx8mq-vpu-g2"; >> + reg = <0x38310000 0x10000>; >> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "g2"; >> + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, >> + <&clk IMX8MQ_CLK_VPU_G2_ROOT>, >> + <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; >> + clock-names = "g1", "g2", "bus"; >> + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, > Can the G1 clock configuration be dropped from the G2 device node and > the G2 clock configuration from the G1 device node? It looks weird that > these devices configure each other's clocks. No because if only one device node is enabled we need to configure the both clocks anyway. Benjamin > > regards > Philipp >
On Fri, 2021-03-26 at 15:33 +0100, Benjamin Gaignard wrote: > > Le 26/03/2021 à 15:24, Philipp Zabel a écrit : > > On Thu, Mar 18, 2021 at 09:20:46AM +0100, Benjamin Gaignard wrote: > > > Split VPU node in two: one for G1 and one for G2 since they are > > > different hardware blocks. > > > Add syscon for hardware control block. > > > Remove reg-names property that is useless. > > > Each VPU node only need one interrupt. > > > > > > Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com> > > > --- > > > version 5: > > > - use syscon instead of VPU reset > > > > > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 43 ++++++++++++++++++----- > > > 1 file changed, 34 insertions(+), 9 deletions(-) > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > > index 17c449e12c2e..b537d153ebbd 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > > @@ -1329,15 +1329,16 @@ usb3_phy1: usb-phy@382f0040 { > > > status = "disabled"; > > > }; > > > > > > - vpu: video-codec@38300000 { > > > + vpu_ctrl: syscon@38320000 { > > > + compatible = "nxp,imx8mq-vpu-ctrl", "syscon"; > > > + reg = <0x38320000 0x10000>; > > > + }; > > > + > > > + vpu_g1: video-codec@38300000 { > > > compatible = "nxp,imx8mq-vpu"; > > > - reg = <0x38300000 0x10000>, > > > - <0x38310000 0x10000>, > > > - <0x38320000 0x10000>; > > > - reg-names = "g1", "g2", "ctrl"; > > > - interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > > > - <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > > > - interrupt-names = "g1", "g2"; > > > + reg = <0x38300000 0x10000>; > > > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; > > > + interrupt-names = "g1"; > > > clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > > > <&clk IMX8MQ_CLK_VPU_G2_ROOT>, > > > <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > > > @@ -1350,9 +1351,33 @@ vpu: video-codec@38300000 { > > > <&clk IMX8MQ_VPU_PLL_OUT>, > > > <&clk IMX8MQ_SYS1_PLL_800M>, > > > <&clk IMX8MQ_VPU_PLL>; > > > - assigned-clock-rates = <600000000>, <600000000>, > > > + assigned-clock-rates = <600000000>, <300000000>, > > I'd like to see this mentioned in the commit message. > > Yes I would do that. > The value comes from the datasheet. > > > > > > + <800000000>, <0>; > > > + power-domains = <&pgc_vpu>; > > > + nxp,imx8mq-vpu-ctrl = <&vpu_ctrl>; > > > + }; > > > + > > > + vpu_g2: video-codec@38310000 { > > > + compatible = "nxp,imx8mq-vpu-g2"; > > > + reg = <0x38310000 0x10000>; > > > + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > > > + interrupt-names = "g2"; > > > + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > > > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>, > > > + <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > > > + clock-names = "g1", "g2", "bus"; > > > + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, > > Can the G1 clock configuration be dropped from the G2 device node and > > the G2 clock configuration from the G1 device node? It looks weird that > > these devices configure each other's clocks. > > No because if only one device node is enabled we need to configure the both > clocks anyway. > Since this is akward, how about adding a comment here in the dtsi to clarify it? Thanks, Ezequiel
The IMX8MQ got two VPUs but until now only G1 has been enabled. This series aim to add the second VPU (aka G2) and provide basic HEVC decoding support. To be able to decode HEVC it is needed to add/update some of the structures in the uapi. In addition of them one HANTRO dedicated control is required to inform the driver of the numbre of bits to skip at the beginning of the slice header. The hardware require to allocate few auxiliary buffers to store the references frame or tile size data. The driver has been tested with fluster test suite stream. For example with this command: ./fluster.py run -ts JCT-VC-HEVC_V1 -d GStreamer-H.265-V4L2SL-Gst1.0 This series depends of the reset rework posted here: https://www.spinics.net/lists/arm-kernel/msg878440.html Finally the both VPUs will have a node the device-tree and be independent from v4l2 point of view. A branch with all the dev is available here: https://gitlab.collabora.com/benjamin.gaignard/for-upstream/-/commits/upstream_g2_v6 version 6: - fix the errors reported by kernel test robot version 5: - use syscon instead of VPU reset driver. - Do not break kernel/DT backward compatibility. - Add documentation for dedicated Hantro control. - Fix the remarks done by Ezequeil (typo, comments, unused function) - Run v4l2-compliance without errors (see below). - Do not add field to distinguish version, check postproc reg instead version 4: - Split the changes in hevc controls in 2 commits to make them easier to review. - Change hantro_codec_ops run() prototype to return errors - Hantro v4l2 dedicated control is now only an integer - rebase on top of VPU reset changes posted here: https://www.spinics.net/lists/arm-kernel/msg878440.html - Various fix from previous remarks - Limit the modifications in API to what the driver needs version 3: - Fix typo in Hantro v4l2 dedicated control - Add documentation for the new structures and fields - Rebased on top of media_tree for-linus-5.12-rc1 tag version 2: - remove all change related to scaling - squash commits to a coherent split - be more verbose about the added fields - fix the comments done by Ezequiel about dma_alloc_coherent usage - fix Dan's comments about control copy, reverse the test logic in tile_buffer_reallocate, rework some goto and return cases. - be more verbose about why I change the bindings - remove all sign-off expect mime since it is confusing - remove useless clocks in VPUs nodes ./v4l2-compliance -m 1 v4l2-compliance 1.21.0-4705, 64 bits, 64-bit time_t v4l2-compliance SHA: 733f7a54f79d 2021-02-03 08:25:49 Compliance test for hantro-vpu device /dev/media1: Media Driver Info: Driver name : hantro-vpu Model : hantro-vpu Serial : Bus info : platform: hantro-vpu Media version : 5.11.0 Hardware revision: 0x00000000 (0) Driver version : 5.11.0 Required ioctls: test MEDIA_IOC_DEVICE_INFO: OK test invalid ioctls: OK Allow for multiple opens: test second /dev/media1 open: OK test MEDIA_IOC_DEVICE_INFO: OK test for unlimited opens: OK Media Controller ioctls: test MEDIA_IOC_G_TOPOLOGY: OK Entities: 3 Interfaces: 1 Pads: 4 Links: 4 test MEDIA_IOC_ENUM_ENTITIES/LINKS: OK test MEDIA_IOC_SETUP_LINK: OK Total for hantro-vpu device /dev/media1: 8, Succeeded: 8, Failed: 0, Warnings: 0 -------------------------------------------------------------------------------- Compliance test for hantro-vpu device /dev/video1: Driver Info: Driver name : hantro-vpu Card type : nxp,imx8mq-vpu-g2-dec Bus info : platform: hantro-vpu Driver version : 5.11.0 Capabilities : 0x84204000 Video Memory-to-Memory Multiplanar Streaming Extended Pix Format Device Capabilities Device Caps : 0x04204000 Video Memory-to-Memory Multiplanar Streaming Extended Pix Format Media Driver Info: Driver name : hantro-vpu Model : hantro-vpu Serial : Bus info : platform: hantro-vpu Media version : 5.11.0 Hardware revision: 0x00000000 (0) Driver version : 5.11.0 Interface Info: ID : 0x0300000c Type : V4L Video Entity Info: ID : 0x00000001 (1) Name : nxp,imx8mq-vpu-g2-dec-source Function : V4L2 I/O Pad 0x01000002 : 0: Source Link 0x02000008: to remote pad 0x1000004 of entity 'nxp,imx8mq-vpu-g2-dec-proc': Data, Enabled, Immutable Required ioctls: test MC information (see 'Media Driver Info' above): OK test VIDIOC_QUERYCAP: OK test invalid ioctls: OK Allow for multiple opens: test second /dev/video1 open: OK test VIDIOC_QUERYCAP: OK test VIDIOC_G/S_PRIORITY: OK test for unlimited opens: OK Debug ioctls: test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported) test VIDIOC_LOG_STATUS: OK (Not Supported) Input ioctls: test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported) test VIDIOC_G/S_FREQUENCY: OK (Not Supported) test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported) test VIDIOC_ENUMAUDIO: OK (Not Supported) test VIDIOC_G/S/ENUMINPUT: OK (Not Supported) test VIDIOC_G/S_AUDIO: OK (Not Supported) Inputs: 0 Audio Inputs: 0 Tuners: 0 Output ioctls: test VIDIOC_G/S_MODULATOR: OK (Not Supported) test VIDIOC_G/S_FREQUENCY: OK (Not Supported) test VIDIOC_ENUMAUDOUT: OK (Not Supported) test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported) test VIDIOC_G/S_AUDOUT: OK (Not Supported) Outputs: 0 Audio Outputs: 0 Modulators: 0 Input/Output configuration ioctls: test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported) test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported) test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported) test VIDIOC_G/S_EDID: OK (Not Supported) Control ioctls: test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK test VIDIOC_QUERYCTRL: OK test VIDIOC_G/S_CTRL: OK test VIDIOC_G/S/TRY_EXT_CTRLS: OK test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK test VIDIOC_G/S_JPEGCOMP: OK (Not Supported) Standard Controls: 8 Private Controls: 1 Format ioctls: test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK test VIDIOC_G/S_PARM: OK (Not Supported) test VIDIOC_G_FBUF: OK (Not Supported) test VIDIOC_G_FMT: OK test VIDIOC_TRY_FMT: OK test VIDIOC_S_FMT: OK test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported) test Cropping: OK (Not Supported) test Composing: OK (Not Supported) test Scaling: OK (Not Supported) Codec ioctls: test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported) test VIDIOC_G_ENC_INDEX: OK (Not Supported) test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported) Buffer ioctls: test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK test VIDIOC_EXPBUF: OK test Requests: OK Total for hantro-vpu device /dev/video1: 46, Succeeded: 46, Failed: 0, Warnings: 0 Grand Total for hantro-vpu device /dev/media1: 54, Succeeded: 54, Failed: 0, Warnings: 0 Benjamin Benjamin Gaignard (13): dt-bindings: mfd: Add 'nxp,imx8mq-vpu-ctrl' to syscon list dt-bindings: media: nxp,imx8mq-vpu: Update the bindings for G2 support media: hantro: Use syscon instead of 'ctrl' register media: hevc: Add fields and flags for hevc PPS media: hevc: Add decode params control media: hantro: change hantro_codec_ops run prototype to return errors media: hantro: Define HEVC codec profiles and supported features media: hantro: Only use postproc when post processed formats are defined media: uapi: Add a control for HANTRO driver media: hantro: handle V4L2_PIX_FMT_HEVC_SLICE control media: hantro: Introduce G2/HEVC decoder media: hantro: IMX8M: add variant for G2/HEVC codec arm64: dts: imx8mq: Add node to G2 hardware .../bindings/media/nxp,imx8mq-vpu.yaml | 53 +- .../devicetree/bindings/mfd/syscon.yaml | 1 + .../userspace-api/media/drivers/hantro.rst | 14 + .../userspace-api/media/drivers/index.rst | 1 + .../media/v4l/ext-ctrls-codec.rst | 108 +++- .../media/v4l/vidioc-queryctrl.rst | 6 + arch/arm64/boot/dts/freescale/imx8mq.dtsi | 43 +- drivers/media/v4l2-core/v4l2-ctrls.c | 26 +- drivers/staging/media/hantro/Makefile | 2 + drivers/staging/media/hantro/hantro.h | 18 +- drivers/staging/media/hantro/hantro_drv.c | 99 ++- .../staging/media/hantro/hantro_g1_h264_dec.c | 10 +- .../media/hantro/hantro_g1_mpeg2_dec.c | 4 +- .../staging/media/hantro/hantro_g1_vp8_dec.c | 6 +- .../staging/media/hantro/hantro_g2_hevc_dec.c | 587 ++++++++++++++++++ drivers/staging/media/hantro/hantro_g2_regs.h | 198 ++++++ .../staging/media/hantro/hantro_h1_jpeg_enc.c | 4 +- drivers/staging/media/hantro/hantro_hevc.c | 324 ++++++++++ drivers/staging/media/hantro/hantro_hw.h | 69 +- .../staging/media/hantro/hantro_postproc.c | 14 + drivers/staging/media/hantro/hantro_v4l2.c | 5 +- drivers/staging/media/hantro/imx8m_vpu_hw.c | 128 +++- .../media/hantro/rk3399_vpu_hw_jpeg_enc.c | 4 +- .../media/hantro/rk3399_vpu_hw_mpeg2_dec.c | 4 +- .../media/hantro/rk3399_vpu_hw_vp8_dec.c | 6 +- drivers/staging/media/sunxi/cedrus/cedrus.c | 6 + drivers/staging/media/sunxi/cedrus/cedrus.h | 1 + .../staging/media/sunxi/cedrus/cedrus_dec.c | 2 + .../staging/media/sunxi/cedrus/cedrus_h265.c | 12 +- include/media/hevc-ctrls.h | 33 +- include/uapi/linux/v4l2-controls.h | 13 + 31 files changed, 1681 insertions(+), 120 deletions(-) create mode 100644 Documentation/userspace-api/media/drivers/hantro.rst create mode 100644 drivers/staging/media/hantro/hantro_g2_hevc_dec.c create mode 100644 drivers/staging/media/hantro/hantro_g2_regs.h create mode 100644 drivers/staging/media/hantro/hantro_hevc.c