| Message ID | 1613114930-1661-1-git-send-email-rnayak@codeaurora.org |
|---|---|
| Headers | show |
| Series | Add binding updates and DT files for SC7280 SoC | expand |
Quoting Rajendra Nayak (2021-02-11 23:28:40) > Add initial device tree support for the SC7280 SoC and the IDP > boards based on this SoC > > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org> > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > new file mode 100644 > index 0000000..428f863 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > @@ -0,0 +1,47 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * sc7280 IDP board device tree source Is it capitalized or not capitalized for SC? > + * > + * Copyright (c) 2021, The Linux Foundation. All rights reserved. > + */ > + > +/dts-v1/; > + > +#include "sc7280.dtsi" > + > +/ { > + model = "Qualcomm Technologies, Inc. SC7280 IDP platform"; Because it is capitalized here.
Quoting Rajendra Nayak (2021-02-11 23:28:42) > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 1fe2eba..7848e88 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -7,6 +7,7 @@ > > #include <dt-bindings/clock/qcom,gcc-sc7280.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > +#include <dt-bindings/soc/qcom,rpmh-rsc.h> > > / { > interrupt-parent = <&intc>; > @@ -30,6 +31,18 @@ > }; > }; > > + reserved_memory: reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + aop_cmd_db_mem: memory@80860000 { > + reg = <0x0 0x80860000 0x0 0x20000>; > + compatible = "qcom,cmd-db"; > + no-map; > + }; > + }; > + > cpus { > #address-cells = <2>; > #size-cells = <0>; > @@ -189,6 +202,19 @@ > }; > }; > > + pdc: interrupt-controller@b220000 { > + compatible = "qcom,sc7280-pdc", "qcom,pdc"; > + reg = <0 0xb220000 0 0x30000>; Can you pad out reg to 8 digits? 0x0b220000 > + qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, > + <55 306 4>, <59 312 3>, <62 374 2>, > + <64 434 2>, <66 438 3>, <69 86 1>, > + <70 520 54>, <124 609 31>, <155 63 1>, > + <156 716 12>; > + #interrupt-cells = <2>; > + interrupt-parent = <&intc>; > + interrupt-controller; > + }; > + > tlmm: pinctrl@f100000 { > compatible = "qcom,sc7280-pinctrl"; > reg = <0 0xf100000 0 0x1000000>; The same applies to the previous patch. Sorry for missing that. > @@ -198,6 +224,7 @@ > interrupt-controller; > #interrupt-cells = <2>; > gpio-ranges = <&tlmm 0 0 175>; > + wakeup-parent = <&pdc>; > > qup_uart5_default: qup-uart5-default { > pins = "gpio46", "gpio47"; > @@ -282,6 +309,23 @@ > status = "disabled"; > }; > }; > + > + apps_rsc: rsc@18200000 { > + compatible = "qcom,rpmh-rsc"; > + reg = <0 0x18200000 0 0x10000>, > + <0 0x18210000 0 0x10000>, > + <0 0x18220000 0 0x10000>; > + reg-names = "drv-0", "drv-1", "drv-2"; > + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; > + qcom,tcs-offset = <0xd00>; > + qcom,drv-id = <2>; > + qcom,tcs-config = <ACTIVE_TCS 2>, > + <SLEEP_TCS 3>, > + <WAKE_TCS 3>, > + <CONTROL_TCS 1>; > + }; > };
Quoting Rajendra Nayak (2021-02-11 23:28:43) > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 7848e88..10851e7 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -6,6 +6,7 @@ > */ > > #include <dt-bindings/clock/qcom,gcc-sc7280.h> > +#include <dt-bindings/clock/qcom,rpmh.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/soc/qcom,rpmh-rsc.h> > > @@ -29,6 +30,42 @@ > clock-frequency = <32000>; > #clock-cells = <0>; > }; > + > + pcie_0_pipe_clk: pcie-0-pipe-clk { > + compatible = "fixed-clock"; > + clock-frequency = <1000>; > + #clock-cells = <0>; > + }; > + > + pcie_1_pipe_clk: pcie-1-pipe-clk { > + compatible = "fixed-clock"; > + clock-frequency = <1000>; > + #clock-cells = <0>; > + }; > + > + ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0-clk { > + compatible = "fixed-clock"; > + clock-frequency = <1000>; > + #clock-cells = <0>; > + }; > + > + ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1-clk { > + compatible = "fixed-clock"; > + clock-frequency = <1000>; > + #clock-cells = <0>; > + }; > + > + ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0-clk { > + compatible = "fixed-clock"; > + clock-frequency = <1000>; > + #clock-cells = <0>; > + }; > + > + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk { > + compatible = "fixed-clock"; > + clock-frequency = <1000>; > + #clock-cells = <0>; > + }; Shouldn't these come from the phys? Why are they being added here? > }; > > reserved_memory: reserved-memory { > @@ -174,6 +211,17 @@ > gcc: clock-controller@100000 { > compatible = "qcom,gcc-sc7280"; > reg = <0 0x00100000 0 0x1f0000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, > + <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>, > + <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>, > + <&ufs_phy_tx_symbol_0_clk>, > + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; If the phys aren't ready then <0> should work. Unless something goes wrong? > + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", > + "pcie_0_pipe_clk", "pcie_1_pipe-clk", > + "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", > + "ufs_phy_tx_symbol_0_clk", > + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; > #clock-cells = <1>; > #reset-cells = <1>; > #power-domain-cells = <1>; > @@ -325,6 +373,13 @@ > <SLEEP_TCS 3>, > <WAKE_TCS 3>, > <CONTROL_TCS 1>; > + > + rpmhcc: qcom,rpmhcc { rpmhcc: clock-controller { > + compatible = "qcom,sc7280-rpmh-clk"; > + clocks = <&xo_board>; > + clock-names = "xo"; > + #clock-cells = <1>; > + }; > }; > }; >
Quoting Rajendra Nayak (2021-02-11 23:28:46) > From: Maulik Shah <mkshah@codeaurora.org> > > Add fw reserved memory area for CPUCP and AOP. Does CPUCP stand for CPU Content Protection? AOP is Always On Processor. It would help if the commit text told us what these acronyms were. > > Signed-off-by: Maulik Shah <mkshah@codeaurora.org> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) >
Quoting Rajendra Nayak (2021-02-11 23:28:48) > From: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > > Add APSS (Application Processor Subsystem) watchdog > DT node for SC7280 SoC. > > Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org> > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Quoting Rajendra Nayak (2021-02-11 23:28:50) > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 8f2002b..3b86052 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -186,12 +207,69 @@ > compatible = "arm,kryo"; > reg = <0x0 0x700>; > enable-method = "psci"; > + cpu-idle-states = <&BIG_CPU_SLEEP_0 > + &BIG_CPU_SLEEP_1 > + &CLUSTER_SLEEP_0>; > next-level-cache = <&L2_700>; > L2_700: l2-cache { > compatible = "cache"; > next-level-cache = <&L3_0>; > }; > }; > + > + idle-states { > + entry-method = "psci"; > + > + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { > + compatible = "arm,idle-state"; > + idle-state-name = "little-power-down"; > + arm,psci-suspend-param = <0x40000003>; > + entry-latency-us = <549>; > + exit-latency-us = <901>; > + min-residency-us = <1774>; Are these preliminary numbers? They're the same as sc7180 from what I can tell, but presumably things changed between SoC versions? > + local-timer-stop; > + }; > + > + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { > + compatible = "arm,idle-state"; > + idle-state-name = "little-rail-power-down"; > + arm,psci-suspend-param = <0x40000004>; > + entry-latency-us = <702>; > + exit-latency-us = <915>; > + min-residency-us = <4001>; > + local-timer-stop; > + }; > + > + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { > + compatible = "arm,idle-state"; > + idle-state-name = "big-power-down"; > + arm,psci-suspend-param = <0x40000003>; > + entry-latency-us = <523>; > + exit-latency-us = <1244>; > + min-residency-us = <2207>;
On 2/23/2021 1:07 PM, Stephen Boyd wrote: > Quoting Rajendra Nayak (2021-02-11 23:28:40) >> Add initial device tree support for the SC7280 SoC and the IDP >> boards based on this SoC >> >> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> >> --- > > Reviewed-by: Stephen Boyd <swboyd@chromium.org> > >> diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts >> new file mode 100644 >> index 0000000..428f863 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts >> @@ -0,0 +1,47 @@ >> +// SPDX-License-Identifier: BSD-3-Clause >> +/* >> + * sc7280 IDP board device tree source > > Is it capitalized or not capitalized for SC? :) I'll be consistent and make it not capitalized everywhere. > >> + * >> + * Copyright (c) 2021, The Linux Foundation. All rights reserved. >> + */ >> + >> +/dts-v1/; >> + >> +#include "sc7280.dtsi" >> + >> +/ { >> + model = "Qualcomm Technologies, Inc. SC7280 IDP platform"; > > Because it is capitalized here. >
On 2/23/2021 1:15 PM, Stephen Boyd wrote: > Quoting Rajendra Nayak (2021-02-11 23:28:46) >> From: Maulik Shah <mkshah@codeaurora.org> >> >> Add fw reserved memory area for CPUCP and AOP. > > Does CPUCP stand for CPU Content Protection? AOP is Always On Processor. > It would help if the commit text told us what these acronyms were. Thanks, I'll expand the acronyms when I re-post. >> >> Signed-off-by: Maulik Shah <mkshah@codeaurora.org> >> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 10 ++++++++++ >> 1 file changed, 10 insertions(+) >>
Hi Stephen, On 2/23/2021 1:19 PM, Stephen Boyd wrote: > Quoting Rajendra Nayak (2021-02-11 23:28:50) >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 8f2002b..3b86052 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -186,12 +207,69 @@ >> compatible = "arm,kryo"; >> reg = <0x0 0x700>; >> enable-method = "psci"; >> + cpu-idle-states = <&BIG_CPU_SLEEP_0 >> + &BIG_CPU_SLEEP_1 >> + &CLUSTER_SLEEP_0>; >> next-level-cache = <&L2_700>; >> L2_700: l2-cache { >> compatible = "cache"; >> next-level-cache = <&L3_0>; >> }; >> }; >> + >> + idle-states { >> + entry-method = "psci"; >> + >> + LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { >> + compatible = "arm,idle-state"; >> + idle-state-name = "little-power-down"; >> + arm,psci-suspend-param = <0x40000003>; >> + entry-latency-us = <549>; >> + exit-latency-us = <901>; >> + min-residency-us = <1774>; > Are these preliminary numbers? They're the same as sc7180 from what I > can tell, but presumably things changed between SoC versions? yes they are preliminary numbers, we are yet to measure on sc7280 and will update later once measured. Thanks, Maulik > >> + local-timer-stop; >> + }; >> + >> + LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 { >> + compatible = "arm,idle-state"; >> + idle-state-name = "little-rail-power-down"; >> + arm,psci-suspend-param = <0x40000004>; >> + entry-latency-us = <702>; >> + exit-latency-us = <915>; >> + min-residency-us = <4001>; >> + local-timer-stop; >> + }; >> + >> + BIG_CPU_SLEEP_0: cpu-sleep-1-0 { >> + compatible = "arm,idle-state"; >> + idle-state-name = "big-power-down"; >> + arm,psci-suspend-param = <0x40000003>; >> + entry-latency-us = <523>; >> + exit-latency-us = <1244>; >> + min-residency-us = <2207>;
Hello Stephen, Thanks for the review. On 2/23/2021 1:13 PM, Stephen Boyd wrote: > Quoting Rajendra Nayak (2021-02-11 23:28:43) >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 7848e88..10851e7 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -6,6 +6,7 @@ >> */ >> >> #include <dt-bindings/clock/qcom,gcc-sc7280.h> >> +#include <dt-bindings/clock/qcom,rpmh.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> #include <dt-bindings/soc/qcom,rpmh-rsc.h> >> >> @@ -29,6 +30,42 @@ >> clock-frequency = <32000>; >> #clock-cells = <0>; >> }; >> + >> + pcie_0_pipe_clk: pcie-0-pipe-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <1000>; >> + #clock-cells = <0>; >> + }; >> + >> + pcie_1_pipe_clk: pcie-1-pipe-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <1000>; >> + #clock-cells = <0>; >> + }; >> + >> + ufs_phy_rx_symbol_0_clk: ufs-phy-rx-symbol-0-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <1000>; >> + #clock-cells = <0>; >> + }; >> + >> + ufs_phy_rx_symbol_1_clk: ufs-phy-rx-symbol-1-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <1000>; >> + #clock-cells = <0>; >> + }; >> + >> + ufs_phy_tx_symbol_0_clk: ufs-phy-tx-symbol-0-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <1000>; >> + #clock-cells = <0>; >> + }; >> + >> + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk { >> + compatible = "fixed-clock"; >> + clock-frequency = <1000>; >> + #clock-cells = <0>; >> + }; > > Shouldn't these come from the phys? Why are they being added here? > Once the phys are added, these could be replaced, that was the reason to add them. >> }; >> >> reserved_memory: reserved-memory { >> @@ -174,6 +211,17 @@ >> gcc: clock-controller@100000 { >> compatible = "qcom,gcc-sc7280"; >> reg = <0 0x00100000 0 0x1f0000>; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, >> + <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, >> + <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>, >> + <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>, >> + <&ufs_phy_tx_symbol_0_clk>, >> + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; > > If the phys aren't ready then <0> should work. Unless something goes > wrong? > Nothing would go wrong if we add <0>, but wanted them to be replaced once the support is added. >> + clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", >> + "pcie_0_pipe_clk", "pcie_1_pipe-clk", >> + "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", >> + "ufs_phy_tx_symbol_0_clk", >> + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; >> #clock-cells = <1>; >> #reset-cells = <1>; >> #power-domain-cells = <1>; >> @@ -325,6 +373,13 @@ >> <SLEEP_TCS 3>, >> <WAKE_TCS 3>, >> <CONTROL_TCS 1>; >> + >> + rpmhcc: qcom,rpmhcc { > > rpmhcc: clock-controller { > Will update in the next patch. >> + compatible = "qcom,sc7280-rpmh-clk"; >> + clocks = <&xo_board>; >> + clock-names = "xo"; >> + #clock-cells = <1>; >> + }; >> }; >> }; >>
Quoting Taniya Das (2021-03-01 09:27:06) > On 2/23/2021 1:13 PM, Stephen Boyd wrote: > > Quoting Rajendra Nayak (2021-02-11 23:28:43) > >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > >> + usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3-phy-wrapper-gcc-usb30-pipe-clk { > >> + compatible = "fixed-clock"; > >> + clock-frequency = <1000>; > >> + #clock-cells = <0>; > >> + }; > > > > Shouldn't these come from the phys? Why are they being added here? > > > > Once the phys are added, these could be replaced, that was the reason to > add them. > > >> }; > >> > >> reserved_memory: reserved-memory { > >> @@ -174,6 +211,17 @@ > >> gcc: clock-controller@100000 { > >> compatible = "qcom,gcc-sc7280"; > >> reg = <0 0x00100000 0 0x1f0000>; > >> + clocks = <&rpmhcc RPMH_CXO_CLK>, > >> + <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, > >> + <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>, > >> + <&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>, > >> + <&ufs_phy_tx_symbol_0_clk>, > >> + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; > > > > If the phys aren't ready then <0> should work. Unless something goes > > wrong? > > > > Nothing would go wrong if we add <0>, but wanted them to be replaced > once the support is added. Please use <0> to indicate that it's missing. Otherwise we may never realize that we should connect it up later.
On Fri 12 Feb 01:28 CST 2021, Rajendra Nayak wrote: > This series includes a few minor binding updates and base device tree > files (to boot to shell) for SC7280 SoC and the IDP board using this SoC. > > The series is dependent on a few driver patches to merge first, for > gcc, rpmhcc and pinctrl > https://lore.kernel.org/patchwork/project/lkml/list/?series=484517 > https://lore.kernel.org/patchwork/project/lkml/list/?series=484489 > https://lore.kernel.org/patchwork/patch/1379831/ > I'm not able to find v2 of this series, but plenty of patches that depends on its content. Do I somehow miss it, or is it coming? Regards, Bjorn > Maulik Shah (3): > arm64: dts: qcom: sc7280: Add RSC and PDC devices > arm64: dts: qcom: Add reserved memory for fw > arm64: dts: qcom: sc7280: Add cpuidle states > > Rajendra Nayak (5): > dt-bindings: arm: qcom: Document SC7280 SoC and board > dt-bindings: firmware: scm: Add SC7280 support > arm64: dts: sc7280: Add basic dts/dtsi files for SC7280 soc > dt-bindings: qcom,pdc: Add compatible for sc7280 > arm64: dts: qcom: SC7280: Add rpmhcc clock controller node > > Sai Prakash Ranjan (4): > dt-bindings: arm-smmu: Add compatible for SC7280 SoC > arm64: dts: qcom: sc7280: Add device node for APPS SMMU > dt-bindings: watchdog: Add compatible for SC7280 SoC > arm64: dts: qcom: sc7280: Add APSS watchdog node > > satya priya (1): > arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280 > > Documentation/devicetree/bindings/arm/qcom.yaml | 6 + > .../devicetree/bindings/firmware/qcom,scm.txt | 1 + > .../bindings/interrupt-controller/qcom,pdc.txt | 1 + > .../devicetree/bindings/iommu/arm,smmu.yaml | 1 + > .../devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + > arch/arm64/boot/dts/qcom/Makefile | 1 + > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 ++ > arch/arm64/boot/dts/qcom/sc7280.dtsi | 596 +++++++++++++++++++++ > 8 files changed, 654 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts > create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi > > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation >
On 3/11/2021 5:43 AM, Bjorn Andersson wrote: > On Fri 12 Feb 01:28 CST 2021, Rajendra Nayak wrote: > >> This series includes a few minor binding updates and base device tree >> files (to boot to shell) for SC7280 SoC and the IDP board using this SoC. >> >> The series is dependent on a few driver patches to merge first, for >> gcc, rpmhcc and pinctrl >> https://lore.kernel.org/patchwork/project/lkml/list/?series=484517 >> https://lore.kernel.org/patchwork/project/lkml/list/?series=484489 >> https://lore.kernel.org/patchwork/patch/1379831/ >> > > I'm not able to find v2 of this series, but plenty of patches that > depends on its content. Do I somehow miss it, or is it coming? I did post v2 [1], and will post v3 shortly addressing some of the feedback from Stephen on v2. I was waiting on the rpmh clock fix to come out [2], which addresses the question about the XO clock frequency [3] in DT [1] https://lore.kernel.org/patchwork/project/lkml/list/?series=487403 [2] https://lore.kernel.org/patchwork/patch/1393159/ [3] https://lore.kernel.org/patchwork/patch/1389019/ > Regards, > Bjorn > >> Maulik Shah (3): >> arm64: dts: qcom: sc7280: Add RSC and PDC devices >> arm64: dts: qcom: Add reserved memory for fw >> arm64: dts: qcom: sc7280: Add cpuidle states >> >> Rajendra Nayak (5): >> dt-bindings: arm: qcom: Document SC7280 SoC and board >> dt-bindings: firmware: scm: Add SC7280 support >> arm64: dts: sc7280: Add basic dts/dtsi files for SC7280 soc >> dt-bindings: qcom,pdc: Add compatible for sc7280 >> arm64: dts: qcom: SC7280: Add rpmhcc clock controller node >> >> Sai Prakash Ranjan (4): >> dt-bindings: arm-smmu: Add compatible for SC7280 SoC >> arm64: dts: qcom: sc7280: Add device node for APPS SMMU >> dt-bindings: watchdog: Add compatible for SC7280 SoC >> arm64: dts: qcom: sc7280: Add APSS watchdog node >> >> satya priya (1): >> arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280 >> >> Documentation/devicetree/bindings/arm/qcom.yaml | 6 + >> .../devicetree/bindings/firmware/qcom,scm.txt | 1 + >> .../bindings/interrupt-controller/qcom,pdc.txt | 1 + >> .../devicetree/bindings/iommu/arm,smmu.yaml | 1 + >> .../devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + >> arch/arm64/boot/dts/qcom/Makefile | 1 + >> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 ++ >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 596 +++++++++++++++++++++ >> 8 files changed, 654 insertions(+) >> create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts >> create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi >> >> -- >> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member >> of Code Aurora Forum, hosted by The Linux Foundation >>
On 3/11/2021 2:45 PM, Rajendra Nayak wrote: > > On 3/11/2021 5:43 AM, Bjorn Andersson wrote: >> On Fri 12 Feb 01:28 CST 2021, Rajendra Nayak wrote: >> >>> This series includes a few minor binding updates and base device tree >>> files (to boot to shell) for SC7280 SoC and the IDP board using this SoC. >>> >>> The series is dependent on a few driver patches to merge first, for >>> gcc, rpmhcc and pinctrl >>> https://lore.kernel.org/patchwork/project/lkml/list/?series=484517 >>> https://lore.kernel.org/patchwork/project/lkml/list/?series=484489 >>> https://lore.kernel.org/patchwork/patch/1379831/ >>> >> >> I'm not able to find v2 of this series, but plenty of patches that >> depends on its content. Do I somehow miss it, or is it coming? > > I did post v2 [1], and will post v3 shortly addressing some of Posted a v3 now [1], also re-based on msm/for-next [1] https://lore.kernel.org/patchwork/project/lkml/list/?series=488871 > the feedback from Stephen on v2. I was waiting on the rpmh clock > fix to come out [2], which addresses the question about the XO clock > frequency [3] in DT > > [1] https://lore.kernel.org/patchwork/project/lkml/list/?series=487403 > [2] https://lore.kernel.org/patchwork/patch/1393159/ > [3] https://lore.kernel.org/patchwork/patch/1389019/ > >> Regards, >> Bjorn >> >>> Maulik Shah (3): >>> arm64: dts: qcom: sc7280: Add RSC and PDC devices >>> arm64: dts: qcom: Add reserved memory for fw >>> arm64: dts: qcom: sc7280: Add cpuidle states >>> >>> Rajendra Nayak (5): >>> dt-bindings: arm: qcom: Document SC7280 SoC and board >>> dt-bindings: firmware: scm: Add SC7280 support >>> arm64: dts: sc7280: Add basic dts/dtsi files for SC7280 soc >>> dt-bindings: qcom,pdc: Add compatible for sc7280 >>> arm64: dts: qcom: SC7280: Add rpmhcc clock controller node >>> >>> Sai Prakash Ranjan (4): >>> dt-bindings: arm-smmu: Add compatible for SC7280 SoC >>> arm64: dts: qcom: sc7280: Add device node for APPS SMMU >>> dt-bindings: watchdog: Add compatible for SC7280 SoC >>> arm64: dts: qcom: sc7280: Add APSS watchdog node >>> >>> satya priya (1): >>> arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280 >>> >>> Documentation/devicetree/bindings/arm/qcom.yaml | 6 + >>> .../devicetree/bindings/firmware/qcom,scm.txt | 1 + >>> .../bindings/interrupt-controller/qcom,pdc.txt | 1 + >>> .../devicetree/bindings/iommu/arm,smmu.yaml | 1 + >>> .../devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + >>> arch/arm64/boot/dts/qcom/Makefile | 1 + >>> arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 ++ >>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 596 +++++++++++++++++++++ >>> 8 files changed, 654 insertions(+) >>> create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts >>> create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi >>> >>> -- >>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member >>> of Code Aurora Forum, hosted by The Linux Foundation >>> >
On Thu 11 Mar 03:15 CST 2021, Rajendra Nayak wrote: > > On 3/11/2021 5:43 AM, Bjorn Andersson wrote: > > On Fri 12 Feb 01:28 CST 2021, Rajendra Nayak wrote: > > > > > This series includes a few minor binding updates and base device tree > > > files (to boot to shell) for SC7280 SoC and the IDP board using this SoC. > > > > > > The series is dependent on a few driver patches to merge first, for > > > gcc, rpmhcc and pinctrl > > > https://lore.kernel.org/patchwork/project/lkml/list/?series=484517 > > > https://lore.kernel.org/patchwork/project/lkml/list/?series=484489 > > > https://lore.kernel.org/patchwork/patch/1379831/ > > > > > > > I'm not able to find v2 of this series, but plenty of patches that > > depends on its content. Do I somehow miss it, or is it coming? > > I did post v2 [1], and will post v3 shortly addressing some of > the feedback from Stephen on v2. Sorry, I had filtered my inbox view a little bit too hard and missed it. v3 looks good to me, so I'll pick it to allow me to land other pending patches on top. Thank you, Bjorn > I was waiting on the rpmh clock fix to come out [2], which addresses > the question about the XO clock frequency [3] in DT > > [1] https://lore.kernel.org/patchwork/project/lkml/list/?series=487403 > [2] https://lore.kernel.org/patchwork/patch/1393159/ > [3] https://lore.kernel.org/patchwork/patch/1389019/ > > > Regards, > > Bjorn > > > > > Maulik Shah (3): > > > arm64: dts: qcom: sc7280: Add RSC and PDC devices > > > arm64: dts: qcom: Add reserved memory for fw > > > arm64: dts: qcom: sc7280: Add cpuidle states > > > > > > Rajendra Nayak (5): > > > dt-bindings: arm: qcom: Document SC7280 SoC and board > > > dt-bindings: firmware: scm: Add SC7280 support > > > arm64: dts: sc7280: Add basic dts/dtsi files for SC7280 soc > > > dt-bindings: qcom,pdc: Add compatible for sc7280 > > > arm64: dts: qcom: SC7280: Add rpmhcc clock controller node > > > > > > Sai Prakash Ranjan (4): > > > dt-bindings: arm-smmu: Add compatible for SC7280 SoC > > > arm64: dts: qcom: sc7280: Add device node for APPS SMMU > > > dt-bindings: watchdog: Add compatible for SC7280 SoC > > > arm64: dts: qcom: sc7280: Add APSS watchdog node > > > > > > satya priya (1): > > > arm64: dts: qcom: sc7280: Add SPMI PMIC arbiter device for SC7280 > > > > > > Documentation/devicetree/bindings/arm/qcom.yaml | 6 + > > > .../devicetree/bindings/firmware/qcom,scm.txt | 1 + > > > .../bindings/interrupt-controller/qcom,pdc.txt | 1 + > > > .../devicetree/bindings/iommu/arm,smmu.yaml | 1 + > > > .../devicetree/bindings/watchdog/qcom-wdt.yaml | 1 + > > > arch/arm64/boot/dts/qcom/Makefile | 1 + > > > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 47 ++ > > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 596 +++++++++++++++++++++ > > > 8 files changed, 654 insertions(+) > > > create mode 100644 arch/arm64/boot/dts/qcom/sc7280-idp.dts > > > create mode 100644 arch/arm64/boot/dts/qcom/sc7280.dtsi > > > > > > -- > > > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > > > of Code Aurora Forum, hosted by The Linux Foundation > > > > > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation