| Message ID | 1605800597-16720-1-git-send-email-claudiu.beznea@microchip.com |
|---|---|
| Headers | show |
| Series | clk: at91: clk-master: re-factor master clock | expand |
I have just noticed that the title of this cover letter is wrong. It should have been: "clk: at91: adapt for dvfs" Please let me know if you want me to send a new version for this update. Thank you, Claudiu On 19.11.2020 17:43, Claudiu Beznea wrote: > Hi, > > SAMA7G5 is capable of DVFS. The supported CPU clock frequencies could be > obtained from CPU PLL. The hardware block diagram for clock feeding the > CPU is as follows: > > +--------+ > +-->|divider1|--> CPU clock > | +--------+ > +--------+ +----------+ | +--------+ > |CPU PLL |-->|prescaller|--+-->|divider0|--> MCK0 clock > +--------+ +----------+ +--------+ > > When switching CPU clock frequencies the MCK0 is also changed by DVFS > driver to avoid its over/under clocking (depending on CPU clock frequency > requested by DVFS algorithms). Some of IPs feed by MCK0 are MCK0 glich > aware, some are not. For this MCK0 was removed from the parents list of > the IPs which are not MCK0 glitch aware (patch 7/11). > > This series adapt AT91 clocks (mostly sam9x60-pll and master clock drivers) > so that runtime changes of these clocks to be allowed. > > The CPU clock was registered from prescaller clock (see above diagram) > and no software control has been added for divider1 because the frequencies > supported by SAMA7G5's CPU could be directly obtained from CPU PLL + > prescaller. > > On top of this series I also added a fix for sama7g5.c code (patch 1/11). > Please let me know if you would like me to send this one separtely (it > would be nice if this fix could be integrated in 5.10). > > Changes were tested on SAMA5D2, SAMA5D3, SAM9X60 and SAMA7G5. > > Thank you, > Claudiu Beznea > > Changes in v6: > - remove if (clk_hw_get_flags(hw) & CLK_SET_RATE_GATE) in patch 10/11 as > we use different clock ops now for pres, div supporting run-time changes > > Changes in v5: > - use separate clk_ops for PLLs and master clock div, pres supporting > run-time changes (patches 6/11, 10/11) > - use unsigned long type for f member of struct typeof(sama7g5_plls) > - document the usage of CLK_IS_CRITICAL > > Changes in v4: > - added Reviewed-by, Tested-by tags forgoten in v3 > > Changes in v3: > - collected Reviewed-by, Tested-by tags > - add patches 4/11, 5/11, 9/11 > - in patch 10/11 use CLK_SET_RATE_GATE on MCK div and MCK pres for all > the platforms except sama7g5 > > Changes in v2: > - s/at91rm9200_mck_lock/at91sam9260_mck_lock in patch 7/8 > > Claudiu Beznea (7): > clk: at91: sama7g5: fix compilation error > clk: at91: clk-sam9x60-pll: allow runtime changes for pll > clk: at91: sama7g5: remove mck0 from parent list of other clocks > clk: at91: sama7g5: decrease lower limit for MCK0 rate > clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz > clk: at91: clk-master: re-factor master clock > clk: at91: sama7g5: register cpu clock > > Eugen Hristev (4): > dt-bindings: clock: at91: add sama7g5 pll defines > clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and > referenced in DT > clk: at91: clk-master: add 5th divisor for mck master > clk: at91: sama7g5: add 5th divisor for mck0 layout and > characteristics > > drivers/clk/at91/at91rm9200.c | 21 ++- > drivers/clk/at91/at91sam9260.c | 26 ++- > drivers/clk/at91/at91sam9g45.c | 32 +++- > drivers/clk/at91/at91sam9n12.c | 36 ++-- > drivers/clk/at91/at91sam9rl.c | 23 ++- > drivers/clk/at91/at91sam9x5.c | 28 ++- > drivers/clk/at91/clk-master.c | 337 ++++++++++++++++++++++++++++++++----- > drivers/clk/at91/clk-sam9x60-pll.c | 145 ++++++++++++++-- > drivers/clk/at91/dt-compat.c | 15 +- > drivers/clk/at91/pmc.h | 22 ++- > drivers/clk/at91/sam9x60.c | 45 +++-- > drivers/clk/at91/sama5d2.c | 42 +++-- > drivers/clk/at91/sama5d3.c | 38 +++-- > drivers/clk/at91/sama5d4.c | 40 +++-- > drivers/clk/at91/sama7g5.c | 223 ++++++++++++++++-------- > include/dt-bindings/clock/at91.h | 11 ++ > 16 files changed, 840 insertions(+), 244 deletions(-) >
Quoting Claudiu Beznea (2020-11-19 07:43:07) > pmc_data_allocate() has been changed. pmc_data_free() was removed. > Adapt the code taking this into consideration. With this the programmable > clocks were also saved in sama7g5_pmc so that they could be later > referenced. > > Fixes: cb783bbbcf54 ("clk: at91: sama7g5: add clock support for sama7g5") > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > Reviewed-by: Tudor Ambarus <tudor.ambarus@microchip.com> > Tested-by: Tudor Ambarus <tudor.ambarus@microchip.com> > --- Applied to clk-next
Quoting Claudiu Beznea (2020-11-19 07:43:09) > From: Eugen Hristev <eugen.hristev@microchip.com> > > Allow SYSPLL and CPUPLL to be referenced as a PMC_TYPE_CORE clock > from phandle in DT. > > Suggested-by: Claudiu Beznea <claudiu.beznea@microchip.com> > Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> > [claudiu.beznea@microchip.com: adapt commit message, add CPU PLL] > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- Applied to clk-next
Quoting Claudiu Beznea (2020-11-19 07:43:10) > From: Eugen Hristev <eugen.hristev@microchip.com> > > clk-master can have 5 divisors with a field width of 3 bits > on some products. > > Change the mask and number of divisors accordingly. > > Reported-by: Mihai Sain <mihai.sain@microchip.com> > Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- Applied to clk-next
Quoting Claudiu Beznea (2020-11-19 07:43:11) > From: Eugen Hristev <eugen.hristev@microchip.com> > > This SoC has the 5th divisor for the mck0 master clock. > Adapt the characteristics accordingly. > > Reported-by: Mihai Sain <mihai.sain@microchip.com> > Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- Applied to clk-next
Quoting Claudiu Beznea (2020-11-19 07:43:12) > Allow runtime frequency changes for PLLs registered with proper flags. > This is necessary for CPU PLL on SAMA7G5 which is used by DVFS. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- Applied to clk-next
Quoting Claudiu Beznea (2020-11-19 07:43:11) > From: Eugen Hristev <eugen.hristev@microchip.com> > > This SoC has the 5th divisor for the mck0 master clock. > Adapt the characteristics accordingly. > > Reported-by: Mihai Sain <mihai.sain@microchip.com> > Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- Applied to clk-next
Quoting Claudiu Beznea (2020-11-19 07:43:12) > Allow runtime frequency changes for PLLs registered with proper flags. > This is necessary for CPU PLL on SAMA7G5 which is used by DVFS. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- Applied to clk-next
Quoting Claudiu Beznea (2020-11-19 07:43:13) > MCK0 is changed at runtime by DVFS. Due to this, since not all IPs > are glitch free aware at MCK0 changes, remove MCK0 from parent list > of other clocks (e.g. generic clock, programmable/system clock, MCKX). > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- Applied to clk-next
Quoting Claudiu Beznea (2020-11-19 07:43:14) > On SAMA7G5 CPU clock is changed at run-time by DVFS. Since MCK0 and > CPU clock shares the same parent clock (CPUPLL clock) the MCK0 is > also changed by DVFS to avoid over/under clocking of MCK0 consumers. > The lower limit is changed to be able to set MCK0 accordingly by > DVFS. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- Applied to clk-next
Quoting Claudiu Beznea (2020-11-19 07:43:15) > Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher > than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at > 1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- Applied to clk-next
Quoting Claudiu Beznea (2020-11-19 07:43:16) > Re-factor master clock driver by splitting it into 2 clocks: prescaller > and divider clocks. Based on registered clock flags the prescaler's rate > could be changed at runtime. This is necessary for platforms supporting > DVFS (e.g. SAMA7G5) where master clock could be changed at run-time. > > Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> > --- Applied to clk-next
Hi, SAMA7G5 is capable of DVFS. The supported CPU clock frequencies could be obtained from CPU PLL. The hardware block diagram for clock feeding the CPU is as follows: +--------+ +-->|divider1|--> CPU clock | +--------+ +--------+ +----------+ | +--------+ |CPU PLL |-->|prescaller|--+-->|divider0|--> MCK0 clock +--------+ +----------+ +--------+ When switching CPU clock frequencies the MCK0 is also changed by DVFS driver to avoid its over/under clocking (depending on CPU clock frequency requested by DVFS algorithms). Some of IPs feed by MCK0 are MCK0 glich aware, some are not. For this MCK0 was removed from the parents list of the IPs which are not MCK0 glitch aware (patch 7/11). This series adapt AT91 clocks (mostly sam9x60-pll and master clock drivers) so that runtime changes of these clocks to be allowed. The CPU clock was registered from prescaller clock (see above diagram) and no software control has been added for divider1 because the frequencies supported by SAMA7G5's CPU could be directly obtained from CPU PLL + prescaller. On top of this series I also added a fix for sama7g5.c code (patch 1/11). Please let me know if you would like me to send this one separtely (it would be nice if this fix could be integrated in 5.10). Changes were tested on SAMA5D2, SAMA5D3, SAM9X60 and SAMA7G5. Thank you, Claudiu Beznea Changes in v6: - remove if (clk_hw_get_flags(hw) & CLK_SET_RATE_GATE) in patch 10/11 as we use different clock ops now for pres, div supporting run-time changes Changes in v5: - use separate clk_ops for PLLs and master clock div, pres supporting run-time changes (patches 6/11, 10/11) - use unsigned long type for f member of struct typeof(sama7g5_plls) - document the usage of CLK_IS_CRITICAL Changes in v4: - added Reviewed-by, Tested-by tags forgoten in v3 Changes in v3: - collected Reviewed-by, Tested-by tags - add patches 4/11, 5/11, 9/11 - in patch 10/11 use CLK_SET_RATE_GATE on MCK div and MCK pres for all the platforms except sama7g5 Changes in v2: - s/at91rm9200_mck_lock/at91sam9260_mck_lock in patch 7/8 Claudiu Beznea (7): clk: at91: sama7g5: fix compilation error clk: at91: clk-sam9x60-pll: allow runtime changes for pll clk: at91: sama7g5: remove mck0 from parent list of other clocks clk: at91: sama7g5: decrease lower limit for MCK0 rate clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHz clk: at91: clk-master: re-factor master clock clk: at91: sama7g5: register cpu clock Eugen Hristev (4): dt-bindings: clock: at91: add sama7g5 pll defines clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DT clk: at91: clk-master: add 5th divisor for mck master clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristics drivers/clk/at91/at91rm9200.c | 21 ++- drivers/clk/at91/at91sam9260.c | 26 ++- drivers/clk/at91/at91sam9g45.c | 32 +++- drivers/clk/at91/at91sam9n12.c | 36 ++-- drivers/clk/at91/at91sam9rl.c | 23 ++- drivers/clk/at91/at91sam9x5.c | 28 ++- drivers/clk/at91/clk-master.c | 337 ++++++++++++++++++++++++++++++++----- drivers/clk/at91/clk-sam9x60-pll.c | 145 ++++++++++++++-- drivers/clk/at91/dt-compat.c | 15 +- drivers/clk/at91/pmc.h | 22 ++- drivers/clk/at91/sam9x60.c | 45 +++-- drivers/clk/at91/sama5d2.c | 42 +++-- drivers/clk/at91/sama5d3.c | 38 +++-- drivers/clk/at91/sama5d4.c | 40 +++-- drivers/clk/at91/sama7g5.c | 223 ++++++++++++++++-------- include/dt-bindings/clock/at91.h | 11 ++ 16 files changed, 840 insertions(+), 244 deletions(-)