Message ID | 20201029112338.28765-1-Lulu_Su@wistron.com |
---|---|
State | Rejected |
Headers | show |
Series | mowgli: Limit slot1 to Gen3 by default | expand |
On 10/29/20 4:53 PM, Lulu Su wrote: > From: LuluTHSu <Lulu_Su@wistron.com> > > Refer to the spec. of mowgli, limit the slot to Gen3 speed. > For mowgli platform spec. Lulu, General process is to post patch to skiboot mailing list and get it accepted in upstream. Then backport patch to applicable stable branches. I dont see this patch posted to upstream. Can you please post it to skiboot mailing list? -Vasant > > Cc: skiboot-stable@lists.ozlabs.org > Signed-off-by: LuluTHSu <Lulu_Su@wistron.com> > --- > hw/phb4.c | 21 +++++++++++++++++++++ > include/phb4.h | 1 + > platforms/astbmc/mowgli.c | 16 ++++++++++++++++ > 3 files changed, 38 insertions(+) > > diff --git a/hw/phb4.c b/hw/phb4.c > index 17a233f..de10bb0 100644 > --- a/hw/phb4.c > +++ b/hw/phb4.c > @@ -2991,6 +2991,27 @@ static unsigned int phb4_get_max_link_speed(struct phb4 *p, struct dt_node *np) > return max_link_speed; > } > > +/* > + * Has the same effect as the ibm,max-link-speed property. > + * i.e. sets the default link speed, while allowing NVRAM > + * overrides, etc to still take effect. > + */ > +void phb4_set_dt_max_link_speed(struct phb4 *p, int new_max) > +{ > + uint64_t scr; > + int max; > + > + /* take into account nvram settings, etc */ > + if (pcie_max_link_speed) > + max = pcie_max_link_speed; > + else > + max = new_max; > + > + scr = phb4_read_reg(p, PHB_PCIE_SCR); > + scr = SETFIELD(PHB_PCIE_SCR_MAXLINKSPEED, scr, max); > + phb4_write_reg(p, PHB_PCIE_SCR, scr); > +} > + > static void phb4_assert_perst(struct pci_slot *slot, bool assert) > { > struct phb4 *p = phb_to_phb4(slot->phb); > diff --git a/include/phb4.h b/include/phb4.h > index abba2d9..47a46b7 100644 > --- a/include/phb4.h > +++ b/include/phb4.h > @@ -259,4 +259,5 @@ static inline int phb4_get_opal_id(unsigned int chip_id, unsigned int index) > > void phb4_pec2_dma_engine_realloc(struct phb4 *p); > > +void phb4_set_dt_max_link_speed(struct phb4 *p, int new_max); > #endif /* __PHB4_H */ > diff --git a/platforms/astbmc/mowgli.c b/platforms/astbmc/mowgli.c > index 9bfe7a4..0246bff 100644 > --- a/platforms/astbmc/mowgli.c > +++ b/platforms/astbmc/mowgli.c > @@ -12,6 +12,8 @@ > #include <psi.h> > #include <npu-regs.h> > #include <secvar.h> > +#include <pci.h> > +#include <phb4.h> > > #include "astbmc.h" > > @@ -71,6 +73,19 @@ static int mowgli_secvar_init(void) > return secvar_main(secboot_tpm_driver, edk2_compatible_v1); > } > > +/* > + * Limit PHB0/(pec0) to gen3 speeds. > + */ > +static void mowgli_setup_phb(struct phb *phb, unsigned int __unused index) > +{ > + struct phb4 *p = phb_to_phb4(phb); > + > + if (p->pec == 0) { > + phb4_set_dt_max_link_speed(p, 3); > + prlog(PR_DEBUG, "Mowgli: Force the PHB%d Speed to Gen3.\n", p->pec); > + } > +} > + > DECLARE_PLATFORM(mowgli) = { > .name = "Mowgli", > .probe = mowgli_probe, > @@ -80,6 +95,7 @@ DECLARE_PLATFORM(mowgli) = { > .bmc = &bmc_plat_ast2500_openbmc, > .pci_get_slot_info = slot_table_get_slot_info, > .pci_probe_complete = check_all_slot_table, > + .pci_setup_phb = mowgli_setup_phb, > .cec_power_down = astbmc_ipmi_power_down, > .cec_reboot = astbmc_ipmi_reboot, > .elog_commit = ipmi_elog_commit, >
On 10/29/20 4:53 PM, Lulu Su wrote: > From: LuluTHSu <Lulu_Su@wistron.com> > > Refer to the spec. of mowgli, limit the slot to Gen3 speed. > For mowgli platform spec. > AFAIK Mowgli will use skiboot v6.7. I guess we don't need to backport this to stable tree. Let me know if you still need this patch in stable tree. -Vasant
diff --git a/hw/phb4.c b/hw/phb4.c index 17a233f..de10bb0 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -2991,6 +2991,27 @@ static unsigned int phb4_get_max_link_speed(struct phb4 *p, struct dt_node *np) return max_link_speed; } +/* + * Has the same effect as the ibm,max-link-speed property. + * i.e. sets the default link speed, while allowing NVRAM + * overrides, etc to still take effect. + */ +void phb4_set_dt_max_link_speed(struct phb4 *p, int new_max) +{ + uint64_t scr; + int max; + + /* take into account nvram settings, etc */ + if (pcie_max_link_speed) + max = pcie_max_link_speed; + else + max = new_max; + + scr = phb4_read_reg(p, PHB_PCIE_SCR); + scr = SETFIELD(PHB_PCIE_SCR_MAXLINKSPEED, scr, max); + phb4_write_reg(p, PHB_PCIE_SCR, scr); +} + static void phb4_assert_perst(struct pci_slot *slot, bool assert) { struct phb4 *p = phb_to_phb4(slot->phb); diff --git a/include/phb4.h b/include/phb4.h index abba2d9..47a46b7 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -259,4 +259,5 @@ static inline int phb4_get_opal_id(unsigned int chip_id, unsigned int index) void phb4_pec2_dma_engine_realloc(struct phb4 *p); +void phb4_set_dt_max_link_speed(struct phb4 *p, int new_max); #endif /* __PHB4_H */ diff --git a/platforms/astbmc/mowgli.c b/platforms/astbmc/mowgli.c index 9bfe7a4..0246bff 100644 --- a/platforms/astbmc/mowgli.c +++ b/platforms/astbmc/mowgli.c @@ -12,6 +12,8 @@ #include <psi.h> #include <npu-regs.h> #include <secvar.h> +#include <pci.h> +#include <phb4.h> #include "astbmc.h" @@ -71,6 +73,19 @@ static int mowgli_secvar_init(void) return secvar_main(secboot_tpm_driver, edk2_compatible_v1); } +/* + * Limit PHB0/(pec0) to gen3 speeds. + */ +static void mowgli_setup_phb(struct phb *phb, unsigned int __unused index) +{ + struct phb4 *p = phb_to_phb4(phb); + + if (p->pec == 0) { + phb4_set_dt_max_link_speed(p, 3); + prlog(PR_DEBUG, "Mowgli: Force the PHB%d Speed to Gen3.\n", p->pec); + } +} + DECLARE_PLATFORM(mowgli) = { .name = "Mowgli", .probe = mowgli_probe, @@ -80,6 +95,7 @@ DECLARE_PLATFORM(mowgli) = { .bmc = &bmc_plat_ast2500_openbmc, .pci_get_slot_info = slot_table_get_slot_info, .pci_probe_complete = check_all_slot_table, + .pci_setup_phb = mowgli_setup_phb, .cec_power_down = astbmc_ipmi_power_down, .cec_reboot = astbmc_ipmi_reboot, .elog_commit = ipmi_elog_commit,