mbox series

[SRU,G/Unstable/OEM-5.6,0/1] Enable LTR for endpoints behind VMD

Message ID 20200922104255.24902-1-kai.heng.feng@canonical.com
Headers show
Series Enable LTR for endpoints behind VMD | expand

Message

Kai-Heng Feng Sept. 22, 2020, 10:42 a.m. UTC 
BugLink: https://bugs.launchpad.net/bugs/1896598

[Impact]
PCIe links behind VMD may not be able to reach ASPM L1.2, because PCIe
Link Tolenrence Reporting doesn't get programmed with a sensible value.

[Fix]
Temporarily hardcode LTR value, which is used by Windows, for NVMe
devices behind VMD.

[Test]
With the patch applied, PCIe links can reach ASPM L1.2, hence the entire
Intel SoC can reach deeper power saving state.

[Regression Potential]
This patch targets specifically Intel Tigerlake VMD bridges, so there
won't be any regression since they are not on the market yet.

Kai-Heng Feng (1):
  UBUNTU: SAUCE: PCI/ASPM: Enable LTR for endpoints behind VMD

 drivers/pci/quirks.c | 49 ++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 45 insertions(+), 4 deletions(-)

Comments

Timo Aaltonen Sept. 22, 2020, 1:25 p.m. UTC | #1 
On 22.9.2020 13.42, Kai-Heng Feng wrote:
> BugLink: https://bugs.launchpad.net/bugs/1896598
> 
> [Impact]
> PCIe links behind VMD may not be able to reach ASPM L1.2, because PCIe
> Link Tolenrence Reporting doesn't get programmed with a sensible value.
> 
> [Fix]
> Temporarily hardcode LTR value, which is used by Windows, for NVMe
> devices behind VMD.
> 
> [Test]
> With the patch applied, PCIe links can reach ASPM L1.2, hence the entire
> Intel SoC can reach deeper power saving state.
> 
> [Regression Potential]
> This patch targets specifically Intel Tigerlake VMD bridges, so there
> won't be any regression since they are not on the market yet.
> 
> Kai-Heng Feng (1):
>    UBUNTU: SAUCE: PCI/ASPM: Enable LTR for endpoints behind VMD
> 
>   drivers/pci/quirks.c | 49 ++++++++++++++++++++++++++++++++++++++++----
>   1 file changed, 45 insertions(+), 4 deletions(-)
> 

looks innocent enough, applied to oem-5.6, thanks
Seth Forshee Sept. 22, 2020, 6:03 p.m. UTC | #2 
On Tue, Sep 22, 2020 at 06:42:53PM +0800, Kai-Heng Feng wrote:
> BugLink: https://bugs.launchpad.net/bugs/1896598
> 
> [Impact]
> PCIe links behind VMD may not be able to reach ASPM L1.2, because PCIe
> Link Tolenrence Reporting doesn't get programmed with a sensible value.
> 
> [Fix]
> Temporarily hardcode LTR value, which is used by Windows, for NVMe
> devices behind VMD.
> 
> [Test]
> With the patch applied, PCIe links can reach ASPM L1.2, hence the entire
> Intel SoC can reach deeper power saving state.
> 
> [Regression Potential]
> This patch targets specifically Intel Tigerlake VMD bridges, so there
> won't be any regression since they are not on the market yet.

Applied to groovy/master-next, thanks!