| Message ID | 1595918641-2325-1-git-send-email-ping.bai@nxp.com |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | [1/3] dt-bindings: arm: fsl: Add imx8mm ddr4 evk board | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | success |
On Tue, 28 Jul 2020 14:43:59 +0800, Jacky Bai wrote: > Add entry for i.MX8MM DDR4 EVK board and update > the comments for imx8mm-evk as it is populated > with LPDDR4. > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > --- > Documentation/devicetree/bindings/arm/fsl.yaml | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > Acked-by: Rob Herring <robh@kernel.org>
Gentle Ping... BR Jacky Bai > -----Original Message----- > From: Jacky Bai > Sent: Tuesday, July 28, 2020 2:44 PM > To: robh+dt@kernel.org; shawnguo@kernel.org; s.hauer@pengutronix.de > Cc: festevam@gmail.com; kernel@pengutronix.de; dl-linux-imx > <linux-imx@nxp.com>; devicetree@vger.kernel.org > Subject: [PATCH 3/3] arm64: dts: imx8mm: Add imx8mm ddr4 evk board > support > > Add the board dts support for i.MX8MM DDR4 EVK board. > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > --- > arch/arm64/boot/dts/freescale/Makefile | 1 + > .../boot/dts/freescale/imx8mm-ddr4-evk.dts | 77 > +++++++++++++++++++ > 2 files changed, 78 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts > > diff --git a/arch/arm64/boot/dts/freescale/Makefile > b/arch/arm64/boot/dts/freescale/Makefile > index a39f0a1723e0..417c552480f2 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += > fsl-lx2160a-qds.dtb > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb diff --git > a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts > b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts > new file mode 100644 > index 000000000000..9cd89182218e > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts > @@ -0,0 +1,77 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2020 NXP > + */ > + > +/dts-v1/; > + > +#include "imx8mm-evk.dtsi" > + > +/ { > + model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board"; > + compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm"; > + > + leds { > + pinctrl-0 = <&pinctrl_gpio_led_2>; > + > + status { > + gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; > + }; > + }; > +}; > + > +&ddrc { > + operating-points-v2 = <&ddrc_opp_table>; > + > + ddrc_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-25M { > + opp-hz = /bits/ 64 <25000000>; > + }; > + > + opp-100M { > + opp-hz = /bits/ 64 <100000000>; > + }; > + > + opp-600M { > + opp-hz = /bits/ 64 <600000000>; > + }; > + }; > +}; > + > +&gpmi { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_gpmi_nand_1>; > + status = "okay"; > + nand-on-flash-bbt; > +}; > + > +&iomuxc { > + pinctrl_gpmi_nand_1: gpmi-nand-1 { > + fsl,pins = < > + MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE > 0x00000096 > + MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B > 0x00000096 > + MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B > 0x00000096 > + MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE > 0x00000096 > + MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 > 0x00000096 > + MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 > 0x00000096 > + MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 > 0x00000096 > + MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 > 0x00000096 > + MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 > 0x00000096 > + MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 > 0x00000096 > + MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 > 0x00000096 > + MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 > 0x00000096 > + MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B > 0x00000096 > + MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B > 0x00000056 > + MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B > 0x00000096 > + MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B > 0x00000096 > + >; > + }; > + > + pinctrl_gpio_led_2: gpioled2grp { > + fsl,pins = < > + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 > + >; > + }; > +}; > -- > 2.26.2
On Tue, Jul 28, 2020 at 02:44:01PM +0800, Jacky Bai wrote: > Add the board dts support for i.MX8MM DDR4 EVK board. > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > --- > arch/arm64/boot/dts/freescale/Makefile | 1 + > .../boot/dts/freescale/imx8mm-ddr4-evk.dts | 77 +++++++++++++++++++ > 2 files changed, 78 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index a39f0a1723e0..417c552480f2 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts > new file mode 100644 > index 000000000000..9cd89182218e > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts > @@ -0,0 +1,77 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2020 NXP > + */ > + > +/dts-v1/; > + > +#include "imx8mm-evk.dtsi" > + > +/ { > + model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board"; > + compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm"; > + > + leds { > + pinctrl-0 = <&pinctrl_gpio_led_2>; > + > + status { > + gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; > + }; > + }; > +}; > + > +&ddrc { > + operating-points-v2 = <&ddrc_opp_table>; > + > + ddrc_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-25M { > + opp-hz = /bits/ 64 <25000000>; > + }; > + > + opp-100M { > + opp-hz = /bits/ 64 <100000000>; > + }; > + > + opp-600M { > + opp-hz = /bits/ 64 <600000000>; > + }; > + }; I'm trying to understand how this ddrc_opp_table is determined. It's defined by SoC/DDR controller or board/DDR chip? > +}; > + > +&gpmi { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_gpmi_nand_1>; > + status = "okay"; Please put 'status' at end of property list. > + nand-on-flash-bbt; > +}; > + > +&iomuxc { > + pinctrl_gpmi_nand_1: gpmi-nand-1 { The suffix "1" isn't really needed, is it? Shawn > + fsl,pins = < > + MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE 0x00000096 > + MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B 0x00000096 > + MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B 0x00000096 > + MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE 0x00000096 > + MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 0x00000096 > + MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 0x00000096 > + MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 0x00000096 > + MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 0x00000096 > + MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 0x00000096 > + MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 0x00000096 > + MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 0x00000096 > + MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 0x00000096 > + MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B 0x00000096 > + MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B 0x00000056 > + MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B 0x00000096 > + MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B 0x00000096 > + >; > + }; > + > + pinctrl_gpio_led_2: gpioled2grp { > + fsl,pins = < > + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 > + >; > + }; > +}; > -- > 2.26.2 >
> -----Original Message----- > From: Shawn Guo [mailto:shawnguo@kernel.org] > Sent: Wednesday, August 19, 2020 9:56 PM > To: Jacky Bai <ping.bai@nxp.com> > Cc: robh+dt@kernel.org; s.hauer@pengutronix.de; festevam@gmail.com; > kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>; > devicetree@vger.kernel.org > Subject: Re: [PATCH 3/3] arm64: dts: imx8mm: Add imx8mm ddr4 evk board > support > > On Tue, Jul 28, 2020 at 02:44:01PM +0800, Jacky Bai wrote: > > Add the board dts support for i.MX8MM DDR4 EVK board. > > > > Signed-off-by: Jacky Bai <ping.bai@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/Makefile | 1 + > > .../boot/dts/freescale/imx8mm-ddr4-evk.dts | 77 > +++++++++++++++++++ > > 2 files changed, 78 insertions(+) > > create mode 100644 > arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts > > > > diff --git a/arch/arm64/boot/dts/freescale/Makefile > > b/arch/arm64/boot/dts/freescale/Makefile > > index a39f0a1723e0..417c552480f2 100644 > > --- a/arch/arm64/boot/dts/freescale/Makefile > > +++ b/arch/arm64/boot/dts/freescale/Makefile > > @@ -29,6 +29,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += > fsl-lx2160a-qds.dtb > > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb > > > > dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb > > +dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb > > dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb diff --git > > a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts > > b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts > > new file mode 100644 > > index 000000000000..9cd89182218e > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts > > @@ -0,0 +1,77 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2020 NXP > > + */ > > + > > +/dts-v1/; > > + > > +#include "imx8mm-evk.dtsi" > > + > > +/ { > > + model = "FSL i.MX8MM DDR4 EVK with CYW43455 WIFI/BT board"; > > + compatible = "fsl,imx8mm-ddr4-evk", "fsl,imx8mm"; > > + > > + leds { > > + pinctrl-0 = <&pinctrl_gpio_led_2>; > > + > > + status { > > + gpios = <&gpio3 4 GPIO_ACTIVE_LOW>; > > + }; > > + }; > > +}; > > + > > +&ddrc { > > + operating-points-v2 = <&ddrc_opp_table>; > > + > > + ddrc_opp_table: opp-table { > > + compatible = "operating-points-v2"; > > + > > + opp-25M { > > + opp-hz = /bits/ 64 <25000000>; > > + }; > > + > > + opp-100M { > > + opp-hz = /bits/ 64 <100000000>; > > + }; > > + > > + opp-600M { > > + opp-hz = /bits/ 64 <600000000>; > > + }; > > + }; > > I'm trying to understand how this ddrc_opp_table is determined. It's > defined by SoC/DDR controller or board/DDR chip? It is related to both SOC DDR controller & the board design. The highest frequency is 600MHz(2400MTS) for DDR4, 750MHz(3000MTS) or 800MHz(3200MTS) for LPDDR4. The lowest frequency also related to DDR type. For LPDDR4, DDRC can run at 25MHz(100MTS), for DDR4, the lowest frequency need to >166MHz. The OPPs defined in dts must be aligned with the OPPs initialized during DDR calibration stage after SOC POR Boot. it seems the ddrc opp table for DDR4 EVK is not correct, I will remove it from this patchset for now, will add it back in a separate patch. > > > +}; > > + > > +&gpmi { > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pinctrl_gpmi_nand_1>; > > + status = "okay"; > > Please put 'status' at end of property list. Thanks, will fix it. > > > + nand-on-flash-bbt; > > +}; > > + > > +&iomuxc { > > + pinctrl_gpmi_nand_1: gpmi-nand-1 { > > The suffix "1" isn't really needed, is it? > Thanks, will fix it in V2. BR Jacky Bai > Shawn > > > + fsl,pins = < > > + MX8MM_IOMUXC_NAND_ALE_RAWNAND_ALE > 0x00000096 > > + MX8MM_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B > 0x00000096 > > + MX8MM_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B > 0x00000096 > > + MX8MM_IOMUXC_NAND_CLE_RAWNAND_CLE > 0x00000096 > > + MX8MM_IOMUXC_NAND_DATA00_RAWNAND_DATA00 > 0x00000096 > > + MX8MM_IOMUXC_NAND_DATA01_RAWNAND_DATA01 > 0x00000096 > > + MX8MM_IOMUXC_NAND_DATA02_RAWNAND_DATA02 > 0x00000096 > > + MX8MM_IOMUXC_NAND_DATA03_RAWNAND_DATA03 > 0x00000096 > > + MX8MM_IOMUXC_NAND_DATA04_RAWNAND_DATA04 > 0x00000096 > > + MX8MM_IOMUXC_NAND_DATA05_RAWNAND_DATA05 > 0x00000096 > > + MX8MM_IOMUXC_NAND_DATA06_RAWNAND_DATA06 > 0x00000096 > > + MX8MM_IOMUXC_NAND_DATA07_RAWNAND_DATA07 > 0x00000096 > > + MX8MM_IOMUXC_NAND_RE_B_RAWNAND_RE_B > 0x00000096 > > + MX8MM_IOMUXC_NAND_READY_B_RAWNAND_READY_B > 0x00000056 > > + MX8MM_IOMUXC_NAND_WE_B_RAWNAND_WE_B > 0x00000096 > > + MX8MM_IOMUXC_NAND_WP_B_RAWNAND_WP_B > 0x00000096 > > + >; > > + }; > > + > > + pinctrl_gpio_led_2: gpioled2grp { > > + fsl,pins = < > > + MX8MM_IOMUXC_NAND_CE3_B_GPIO3_IO4 0x19 > > + >; > > + }; > > +}; > > -- > > 2.26.2 > >
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index f63895c8ce2d..7c1cb8953342 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -341,7 +341,8 @@ properties: - description: i.MX8MM based Boards items: - enum: - - fsl,imx8mm-evk # i.MX8MM EVK Board + - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board + - fsl,imx8mm-evk # i.MX8MM LPDDR4 EVK Board - const: fsl,imx8mm - description: i.MX8MN based Boards
Add entry for i.MX8MM DDR4 EVK board and update the comments for imx8mm-evk as it is populated with LPDDR4. Signed-off-by: Jacky Bai <ping.bai@nxp.com> --- Documentation/devicetree/bindings/arm/fsl.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)