Message ID | 20200819080225.4267-5-linux@fw-web.de |
---|---|
State | Superseded |
Delegated to: | Marek Vasut |
Headers | show |
Series | Add MTK AHCI driver, BPI-R64 dts and USB-Nodes for mt7622/mt7623 | expand |
Hi Frank, Thanks your for your patches. some suggestions for coding style. On Wed, 2020-08-19 at 10:02 +0200, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > bind reset controller to pciesys > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > --- > drivers/clk/mediatek/clk-mt7622.c | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c > index bd86b5b974..d53ed69189 100644 > --- a/drivers/clk/mediatek/clk-mt7622.c > +++ b/drivers/clk/mediatek/clk-mt7622.c > @@ -594,6 +594,20 @@ static int mt7622_pciesys_probe(struct udevice *dev) > return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs); > } > > +static int mt7622_pciesys_bind(struct udevice *dev) > +{ > + int ret = 0; > + > + if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) { > +// PCIESYS uses in linux also 0x34 = ETHSYS reset controller No need to add special comments that are not easy to understand, and please uses "/* */" instead of "//". Thanks, Best Regards, Sam Shih
Hi > Gesendet: Mittwoch, 19. August 2020 um 10:33 Uhr > Von: "Sam Shih" <sam.shih@mediatek.com> > > + if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) { > > +// PCIESYS uses in linux also 0x34 = ETHSYS reset controller > > No need to add special comments that are not easy to understand, > and please uses "/* */" instead of "//". should i remove it or use other words? maybe we can use mt7622_ethsys_bind for binding pciesys? basicly it's same code regards Frank
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c index bd86b5b974..d53ed69189 100644 --- a/drivers/clk/mediatek/clk-mt7622.c +++ b/drivers/clk/mediatek/clk-mt7622.c @@ -594,6 +594,20 @@ static int mt7622_pciesys_probe(struct udevice *dev) return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, pcie_cgs); } +static int mt7622_pciesys_bind(struct udevice *dev) +{ + int ret = 0; + + if (IS_ENABLED(CONFIG_RESET_MEDIATEK)) { +// PCIESYS uses in linux also 0x34 = ETHSYS reset controller + ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1); + if (ret) + debug("Warning: failed to bind reset controller\n"); + } + + return ret; +} + static int mt7622_ethsys_probe(struct udevice *dev) { return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs); @@ -710,6 +724,7 @@ U_BOOT_DRIVER(mtk_clk_pciesys) = { .id = UCLASS_CLK, .of_match = mt7622_pciesys_compat, .probe = mt7622_pciesys_probe, + .bind = mt7622_pciesys_bind, .priv_auto_alloc_size = sizeof(struct mtk_cg_priv), .ops = &mtk_clk_gate_ops, };