Message ID | 20200819080225.4267-10-linux@fw-web.de |
---|---|
State | Superseded |
Delegated to: | Marek Vasut |
Headers | show |
Series | Add MTK AHCI driver, BPI-R64 dts and USB-Nodes for mt7622/mt7623 | expand |
On Wed, 2020-08-19 at 10:02 +0200, Frank Wunderlich wrote: > From: Frank Wunderlich <frank-w@public-files.de> > > asm_sel is for switching between sata and pcie mode > on r64 there is GPIO90 connected to ASM1480 which > switches RX/TX pairs to PCIe/SATA connector > output-low means sata-controller is active > > Signed-off-by: Frank Wunderlich <frank-w@public-files.de> > --- > arch/arm/dts/mt7622-bananapi-bpi-r64.dts | 9 +++++++ > arch/arm/dts/mt7622.dtsi | 31 ++++++++++++++++++++++++ > 2 files changed, 40 insertions(+) > > diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts > index 768f15bc2c..c36ec8f8d0 100644 > --- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts > +++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts > @@ -204,3 +204,12 @@ > full-duplex; > }; > }; > + > +&gpio { > + /*gpio 90 for setting mode to sata*/ > + asm_sel { > + gpio-hog; > + gpios = <90 GPIO_ACTIVE_HIGH>; > + output-low; > + }; > +}; > diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi > index fec071643e..6b4260407e 100644 > --- a/arch/arm/dts/mt7622.dtsi > +++ b/arch/arm/dts/mt7622.dtsi > @@ -10,6 +10,7 @@ > #include <dt-bindings/power/mt7629-power.h> > #include <dt-bindings/reset/mt7629-reset.h> > #include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/phy/phy.h> > > / { > compatible = "mediatek,mt7622"; > @@ -270,6 +271,36 @@ > }; > }; > > + sata: sata@1a200000 { > + compatible = "mediatek,mtk-ahci"; > + reg = <0x1a200000 0x1100>; > + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, > + <&pciesys MT7622_SATA_PHY_SW_RST>, > + <&pciesys MT7622_SATA_PHY_REG_RST>; > + reset-names = "axi", "sw", "reg"; > + mediatek,phy-mode = <&pciesys>; > + ports-implemented = <0x1>; > + phys = <&sata_port PHY_TYPE_SATA>; > + phy-names = "sata-phy"; > + status = "okay"; > + }; > + > + sata_phy: sata-phy@1a243000 { > + compatible = "mediatek,generic-tphy-v1"; > + #address-cells = <1>; > + #size-cells = <1>; > + ranges; we can use ranges with parameters if you send next version, otherwise no change is also fine to me. ranges=<0 0x1a243000 0x100>; > + status = "okay"; > + > + sata_port: sata-phy@1a243000 { > + reg = <0x1a243000 0x0100>; sata_port: sata-phy@0 { reg = <0x0 0x0100>; > + clocks = <&topckgen CLK_TOP_ETH_500M>; > + clock-names = "ref"; > + #phy-cells = <1>; > + status = "okay"; > + }; > + }; For phy part, Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com> thanks > + > ethsys: syscon@1b000000 { > compatible = "mediatek,mt7622-ethsys", "syscon"; > reg = <0x1b000000 0x1000>;
Hi > Gesendet: Mittwoch, 19. August 2020 um 10:54 Uhr > Von: "Chunfeng Yun" <chunfeng.yun@mediatek.com> > > + sata_phy: sata-phy@1a243000 { > > + compatible = "mediatek,generic-tphy-v1"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + ranges; > we can use ranges with parameters if you send next version, otherwise no > change is also fine to me. > > ranges=<0 0x1a243000 0x100>; i took the dts-part from linux where ranges is also empty https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/mediatek/mt7622.dtsi#L880 why should ranges have a value when i recently removed the reg (after making it optional)? > For phy part, > Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com> any issues in sata-node/gpio-hog? regards Frank
On Wed, 2020-08-19 at 12:58 +0200, Frank Wunderlich wrote: > Hi > > > Gesendet: Mittwoch, 19. August 2020 um 10:54 Uhr > > Von: "Chunfeng Yun" <chunfeng.yun@mediatek.com> > > > + sata_phy: sata-phy@1a243000 { > > > + compatible = "mediatek,generic-tphy-v1"; > > > + #address-cells = <1>; > > > + #size-cells = <1>; > > > + ranges; > > we can use ranges with parameters if you send next version, otherwise no > > change is also fine to me. > > > > ranges=<0 0x1a243000 0x100>; > > i took the dts-part from linux where ranges is also empty > > https://elixir.bootlin.com/linux/latest/source/arch/arm64/boot/dts/mediatek/mt7622.dtsi#L880 > I think it follows the early dt-binding doc of tphy, I modify it later. > why should ranges have a value when i recently removed the reg (after making it optional)? Both are ok, but prefer to use translation way:) Without shared registers, it's simple and clear to use address translation from parent-bus-address to child-bus-address. e.g. subnode: usb-phy@0, usb-phy@1000, they tell us the offset at the same time. > > > For phy part, > > Reviewed-by: Chunfeng Yun <chunfeng.yun@mediatek.com> > > any issues in sata-node/gpio-hog? Also looks good to me > > regards Frank
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts index 768f15bc2c..c36ec8f8d0 100644 --- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts @@ -204,3 +204,12 @@ full-duplex; }; }; + +&gpio { + /*gpio 90 for setting mode to sata*/ + asm_sel { + gpio-hog; + gpios = <90 GPIO_ACTIVE_HIGH>; + output-low; + }; +}; diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi index fec071643e..6b4260407e 100644 --- a/arch/arm/dts/mt7622.dtsi +++ b/arch/arm/dts/mt7622.dtsi @@ -10,6 +10,7 @@ #include <dt-bindings/power/mt7629-power.h> #include <dt-bindings/reset/mt7629-reset.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> / { compatible = "mediatek,mt7622"; @@ -270,6 +271,36 @@ }; }; + sata: sata@1a200000 { + compatible = "mediatek,mtk-ahci"; + reg = <0x1a200000 0x1100>; + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>, + <&pciesys MT7622_SATA_PHY_SW_RST>, + <&pciesys MT7622_SATA_PHY_REG_RST>; + reset-names = "axi", "sw", "reg"; + mediatek,phy-mode = <&pciesys>; + ports-implemented = <0x1>; + phys = <&sata_port PHY_TYPE_SATA>; + phy-names = "sata-phy"; + status = "okay"; + }; + + sata_phy: sata-phy@1a243000 { + compatible = "mediatek,generic-tphy-v1"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "okay"; + + sata_port: sata-phy@1a243000 { + reg = <0x1a243000 0x0100>; + clocks = <&topckgen CLK_TOP_ETH_500M>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; + }; + ethsys: syscon@1b000000 { compatible = "mediatek,mt7622-ethsys", "syscon"; reg = <0x1b000000 0x1000>;