Message ID | 1596815755-10994-1-git-send-email-min.li.xe@renesas.com |
---|---|
State | Changes Requested |
Delegated to: | David Miller |
Headers | show |
Series | [net,1/4] ptp: ptp_idt82p33: update to support adjphase | expand |
Hi, Thank you for the patch! Yet something to improve: [auto build test ERROR on net/master] url: https://github.com/0day-ci/linux/commits/min-li-xe-renesas-com/ptp-ptp_idt82p33-update-to-support-adjphase/20200808-000545 base: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git 8912fd6a61d7474ea9b43be93f136034d28868d5 config: i386-randconfig-s001-20200807 (attached as .config) compiler: gcc-9 (Debian 9.3.0-15) 9.3.0 reproduce: # apt-get install sparse # sparse version: v0.6.2-118-ge1578773-dirty # save the attached .config to linux build tree make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' ARCH=i386 If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot <lkp@intel.com> All errors (new ones prefixed by >>): ld: drivers/ptp/ptp_idt82p33.o: in function `idt82p33_adjwritephase': >> drivers/ptp/ptp_idt82p33.c:695: undefined reference to `__divdi3' vim +695 drivers/ptp/ptp_idt82p33.c 676 677 static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 offsetNs) 678 { 679 struct idt82p33_channel *channel = 680 container_of(ptp, struct idt82p33_channel, caps); 681 struct idt82p33 *idt82p33 = channel->idt82p33; 682 s64 offsetInFs; 683 s64 offsetRegVal; 684 u8 val[4] = {0}; 685 int err; 686 687 offsetInFs = (s64)(-offsetNs) * 1000000; 688 689 if (offsetInFs > WRITE_PHASE_OFFSET_LIMIT) 690 offsetInFs = WRITE_PHASE_OFFSET_LIMIT; 691 else if (offsetInFs < -WRITE_PHASE_OFFSET_LIMIT) 692 offsetInFs = -WRITE_PHASE_OFFSET_LIMIT; 693 694 /* Convert from phaseOffsetInFs to register value */ > 695 offsetRegVal = ((offsetInFs * 1000) / IDT_T0DPLL_PHASE_RESOL); 696 697 val[0] = offsetRegVal & 0xFF; 698 val[1] = (offsetRegVal >> 8) & 0xFF; 699 val[2] = (offsetRegVal >> 16) & 0xFF; 700 val[3] = (offsetRegVal >> 24) & 0x1F; 701 val[3] |= PH_OFFSET_EN; 702 703 mutex_lock(&idt82p33->reg_lock); 704 705 err = idt82p33_dpll_set_mode(channel, PLL_MODE_WPH); 706 if (err) { 707 dev_err(&idt82p33->client->dev, 708 "Failed at line %d in func %s!\n", 709 __LINE__, 710 __func__); 711 goto out; 712 } 713 714 err = idt82p33_write(idt82p33, channel->dpll_phase_cnfg, val, 715 sizeof(val)); 716 717 out: 718 mutex_unlock(&idt82p33->reg_lock); 719 return err; 720 } 721 --- 0-DAY CI Kernel Test Service, Intel Corporation https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
Hi,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on net/master]
url: https://github.com/0day-ci/linux/commits/min-li-xe-renesas-com/ptp-ptp_idt82p33-update-to-support-adjphase/20200808-000545
base: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net.git 8912fd6a61d7474ea9b43be93f136034d28868d5
config: h8300-allyesconfig (attached as .config)
compiler: h8300-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=h8300
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
h8300-linux-ld: drivers/ptp/ptp_idt82p33.o: in function `.L28':
>> ptp_idt82p33.c:(.text+0x3c5): undefined reference to `__divdi3'
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
Hi David/Richard When you have time, can you take a look at this change? Thanks Min -----Original Message----- From: min.li.xe@renesas.com <min.li.xe@renesas.com> Sent: August 7, 2020 11:56 AM To: richardcochran@gmail.com Cc: netdev@vger.kernel.org; linux-kernel@vger.kernel.org; Min Li <min.li.xe@renesas.com> Subject: [PATCH net 1/4] ptp: ptp_idt82p33: update to support adjphase From: Min Li <min.li.xe@renesas.com> Add adjphase support for idt82p33xxx synchronization management unit. Also fix n_per_out to the actual number of outputs. Changes since v1: - Break into small changes Signed-off-by: Min Li <min.li.xe@renesas.com> --- drivers/ptp/ptp_idt82p33.c | 48 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/drivers/ptp/ptp_idt82p33.c b/drivers/ptp/ptp_idt82p33.c index 179f6c4..bd1fbcd 100644 --- a/drivers/ptp/ptp_idt82p33.c +++ b/drivers/ptp/ptp_idt82p33.c @@ -674,6 +674,51 @@ static int idt82p33_enable(struct ptp_clock_info *ptp, return err; } +static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 +offsetNs) { + struct idt82p33_channel *channel = + container_of(ptp, struct idt82p33_channel, caps); + struct idt82p33 *idt82p33 = channel->idt82p33; + s64 offsetInFs; + s64 offsetRegVal; + u8 val[4] = {0}; + int err; + + offsetInFs = (s64)(-offsetNs) * 1000000; + + if (offsetInFs > WRITE_PHASE_OFFSET_LIMIT) + offsetInFs = WRITE_PHASE_OFFSET_LIMIT; + else if (offsetInFs < -WRITE_PHASE_OFFSET_LIMIT) + offsetInFs = -WRITE_PHASE_OFFSET_LIMIT; + + /* Convert from phaseOffsetInFs to register value */ + offsetRegVal = ((offsetInFs * 1000) / IDT_T0DPLL_PHASE_RESOL); + + val[0] = offsetRegVal & 0xFF; + val[1] = (offsetRegVal >> 8) & 0xFF; + val[2] = (offsetRegVal >> 16) & 0xFF; + val[3] = (offsetRegVal >> 24) & 0x1F; + val[3] |= PH_OFFSET_EN; + + mutex_lock(&idt82p33->reg_lock); + + err = idt82p33_dpll_set_mode(channel, PLL_MODE_WPH); + if (err) { + dev_err(&idt82p33->client->dev, + "Failed at line %d in func %s!\n", + __LINE__, + __func__); + goto out; + } + + err = idt82p33_write(idt82p33, channel->dpll_phase_cnfg, val, + sizeof(val)); + +out: + mutex_unlock(&idt82p33->reg_lock); + return err; +} + static int idt82p33_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) { struct idt82p33_channel *channel = @@ -784,6 +829,8 @@ static void idt82p33_caps_init(struct ptp_clock_info *caps) { caps->owner = THIS_MODULE; caps->max_adj = 92000; + caps->n_per_out = 11; + caps->adjphase = idt82p33_adjwritephase; caps->adjfine = idt82p33_adjfine; caps->adjtime = idt82p33_adjtime; caps->gettime64 = idt82p33_gettime; @@ -810,7 +857,6 @@ static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index) idt82p33_caps_init(&channel->caps); snprintf(channel->caps.name, sizeof(channel->caps.name), "IDT 82P33 PLL%u", index); - channel->caps.n_per_out = hweight8(channel->output_mask); err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO); if (err) -- 2.7.4
On Thu, Oct 15, 2020 at 07:30:38PM +0000, Min Li wrote:
> When you have time, can you take a look at this change? Thanks
Min,
I think your series was posted during a time when net-next was closed.
Please report the series.
Thanks,
Richard
Hi! > +static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 > +offsetNs) { adj_write_phase? > + struct idt82p33_channel *channel = > + container_of(ptp, struct idt82p33_channel, caps); > + struct idt82p33 *idt82p33 = channel->idt82p33; > + s64 offsetInFs; > + s64 offsetRegVal; > + u8 val[4] = {0}; > + int err; > + > + offsetInFs = (s64)(-offsetNs) * 1000000; > + > + if (offsetInFs > WRITE_PHASE_OFFSET_LIMIT) > + offsetInFs = WRITE_PHASE_OFFSET_LIMIT; > + else if (offsetInFs < -WRITE_PHASE_OFFSET_LIMIT) > + offsetInFs = -WRITE_PHASE_OFFSET_LIMIT; I'm sure we have macro for this. > + /* Convert from phaseOffsetInFs to register value */ > + offsetRegVal = ((offsetInFs * 1000) / IDT_T0DPLL_PHASE_RESOL); > + > + val[0] = offsetRegVal & 0xFF; > + val[1] = (offsetRegVal >> 8) & 0xFF; > + val[2] = (offsetRegVal >> 16) & 0xFF; > + val[3] = (offsetRegVal >> 24) & 0x1F; > + val[3] |= PH_OFFSET_EN; ThisIsReally far away from usual coding style. Best regards, Pavel
diff --git a/drivers/ptp/ptp_idt82p33.c b/drivers/ptp/ptp_idt82p33.c index 179f6c4..bd1fbcd 100644 --- a/drivers/ptp/ptp_idt82p33.c +++ b/drivers/ptp/ptp_idt82p33.c @@ -674,6 +674,51 @@ static int idt82p33_enable(struct ptp_clock_info *ptp, return err; } +static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 offsetNs) +{ + struct idt82p33_channel *channel = + container_of(ptp, struct idt82p33_channel, caps); + struct idt82p33 *idt82p33 = channel->idt82p33; + s64 offsetInFs; + s64 offsetRegVal; + u8 val[4] = {0}; + int err; + + offsetInFs = (s64)(-offsetNs) * 1000000; + + if (offsetInFs > WRITE_PHASE_OFFSET_LIMIT) + offsetInFs = WRITE_PHASE_OFFSET_LIMIT; + else if (offsetInFs < -WRITE_PHASE_OFFSET_LIMIT) + offsetInFs = -WRITE_PHASE_OFFSET_LIMIT; + + /* Convert from phaseOffsetInFs to register value */ + offsetRegVal = ((offsetInFs * 1000) / IDT_T0DPLL_PHASE_RESOL); + + val[0] = offsetRegVal & 0xFF; + val[1] = (offsetRegVal >> 8) & 0xFF; + val[2] = (offsetRegVal >> 16) & 0xFF; + val[3] = (offsetRegVal >> 24) & 0x1F; + val[3] |= PH_OFFSET_EN; + + mutex_lock(&idt82p33->reg_lock); + + err = idt82p33_dpll_set_mode(channel, PLL_MODE_WPH); + if (err) { + dev_err(&idt82p33->client->dev, + "Failed at line %d in func %s!\n", + __LINE__, + __func__); + goto out; + } + + err = idt82p33_write(idt82p33, channel->dpll_phase_cnfg, val, + sizeof(val)); + +out: + mutex_unlock(&idt82p33->reg_lock); + return err; +} + static int idt82p33_adjfine(struct ptp_clock_info *ptp, long scaled_ppm) { struct idt82p33_channel *channel = @@ -784,6 +829,8 @@ static void idt82p33_caps_init(struct ptp_clock_info *caps) { caps->owner = THIS_MODULE; caps->max_adj = 92000; + caps->n_per_out = 11; + caps->adjphase = idt82p33_adjwritephase; caps->adjfine = idt82p33_adjfine; caps->adjtime = idt82p33_adjtime; caps->gettime64 = idt82p33_gettime; @@ -810,7 +857,6 @@ static int idt82p33_enable_channel(struct idt82p33 *idt82p33, u32 index) idt82p33_caps_init(&channel->caps); snprintf(channel->caps.name, sizeof(channel->caps.name), "IDT 82P33 PLL%u", index); - channel->caps.n_per_out = hweight8(channel->output_mask); err = idt82p33_dpll_set_mode(channel, PLL_MODE_DCO); if (err)