Message ID | 1596015374-25821-1-git-send-email-sagar.kadam@sifive.com |
---|---|
Headers | show |
Series | add DM based reset driver for SiFive SoC's | expand |
Hi Rick, > -----Original Message----- > From: Sagar Kadam <sagar.kadam@sifive.com> > Sent: Wednesday, July 29, 2020 3:06 PM > To: u-boot@lists.denx.de > Cc: rick@andestech.com; Paul Walmsley ( Sifive) <paul.walmsley@sifive.com>; > palmer@dabbelt.com; anup.patel@wdc.com; atish.patra@wdc.com; > lukma@denx.de; Pragnesh Patel <pragnesh.patel@sifive.com>; > bin.meng@windriver.com; jagan@amarulasolutions.com; sjg@chromium.org; > twoerner@gmail.com; mbrugger@suse.com; Eugeniy.Paltsev@synopsys.com; > seanga2@gmail.com; patrick@blueri.se; nsaenzjulienne@suse.de; > weijie.gao@mediatek.com; festevam@gmail.com; Sagar Kadam > <sagar.kadam@sifive.com> > Subject: [PATCH v5 0/5] add DM based reset driver for SiFive SoC's > > The FU540-C000 support in U-Boot is missing DM based reset driver, and is > handling reset's to sub-system within the prci driver itself. > The series here adds a generic DM reset driver for SiFive SoC's so as to leverage > the U-Boot's reset framework and binds the reset driver with prci driver. > The PRCI driver takes care of triggering the consumers reset signals > appropriately. > > Patch 1: Add necessary dt indexes for device reset register. > Patch 2: Update macro's to use common dt indexes from binding header. > Patch 3: Add reset producer and consumer entries within the device tree. > Patch 4: Add reset dm driver and bind it within prci module. > Patch 5: Add Kconfig, Makefile entries and enable the driver > > This series is re-based on u-boot-riscv top commit 3b191c56c841 ("Merge > branch '2020-07-28-Kconfig-migrations'") > > History: > ========================== > V5: > -Rebased the series on u-boot-riscv/master. > A gentle reminder to pull in this series. Thanks & BR, Sagar > V4: > -Rebased the series to u-boot/master. > > V3: > -Add reset indexes in separate dt binding header instead of updating the clock > dt binding header which is synced from Linux > > V2: > -Removed extra character in commit log of 2nd patch > > V1: > -Base version. > > Sagar Shrikant Kadam (5): > dt-bindings: prci: add indexes for reset signals available in prci > fu540: prci: use common reset indexes defined in binding header > fu540: dtsi: add reset producer and consumer entries > sifive: reset: add DM based reset driver for SiFive SoC's > configs: reset: fu540: enable dm reset framework for SiFive > > arch/riscv/dts/fu540-c000-u-boot.dtsi | 12 +++ > arch/riscv/include/asm/arch-fu540/reset.h | 13 +++ > configs/sifive_fu540_defconfig | 2 + > drivers/clk/sifive/fu540-prci.c | 90 ++++++++++++++------ > drivers/reset/Kconfig | 9 ++ > drivers/reset/Makefile | 1 + > drivers/reset/reset-sifive.c | 118 ++++++++++++++++++++++++++ > include/dt-bindings/reset/sifive-fu540-prci.h | 19 +++++ > 8 files changed, 239 insertions(+), 25 deletions(-) create mode 100644 > arch/riscv/include/asm/arch-fu540/reset.h > create mode 100644 drivers/reset/reset-sifive.c create mode 100644 > include/dt-bindings/reset/sifive-fu540-prci.h > > -- > 2.7.4
<rick@andestech.com> 於 2020年8月3日 週一 上午11:05寫道: > > > > -----Original Message----- > From: Sagar Kadam [mailto:sagar.kadam@sifive.com] > Sent: Friday, July 31, 2020 9:15 PM > To: u-boot@lists.denx.de > Cc: Rick Jian-Zhi Chen(陳建志); Paul Walmsley ( Sifive); palmer@dabbelt.com; anup.patel@wdc.com; atish.patra@wdc.com; lukma@denx.de; Pragnesh Patel; bin.meng@windriver.com; jagan@amarulasolutions.com; sjg@chromium.org; twoerner@gmail.com; mbrugger@suse.com; Eugeniy.Paltsev@synopsys.com; seanga2@gmail.com; patrick@blueri.se; nsaenzjulienne@suse.de; weijie.gao@mediatek.com; festevam@gmail.com > Subject: RE: [PATCH v5 0/5] add DM based reset driver for SiFive SoC's > > Hi Rick, > > > -----Original Message----- > > From: Sagar Kadam <sagar.kadam@sifive.com> > > Sent: Wednesday, July 29, 2020 3:06 PM > > To: u-boot@lists.denx.de > > Cc: rick@andestech.com; Paul Walmsley ( Sifive) > > <paul.walmsley@sifive.com>; palmer@dabbelt.com; anup.patel@wdc.com; > > atish.patra@wdc.com; lukma@denx.de; Pragnesh Patel > > <pragnesh.patel@sifive.com>; bin.meng@windriver.com; > > jagan@amarulasolutions.com; sjg@chromium.org; twoerner@gmail.com; > > mbrugger@suse.com; Eugeniy.Paltsev@synopsys.com; seanga2@gmail.com; > > patrick@blueri.se; nsaenzjulienne@suse.de; weijie.gao@mediatek.com; > > festevam@gmail.com; Sagar Kadam <sagar.kadam@sifive.com> > > Subject: [PATCH v5 0/5] add DM based reset driver for SiFive SoC's > > > > The FU540-C000 support in U-Boot is missing DM based reset driver, and > > is handling reset's to sub-system within the prci driver itself. > > The series here adds a generic DM reset driver for SiFive SoC's so as > > to leverage the U-Boot's reset framework and binds the reset driver with prci driver. > > The PRCI driver takes care of triggering the consumers reset signals > > appropriately. > > > > Patch 1: Add necessary dt indexes for device reset register. > > Patch 2: Update macro's to use common dt indexes from binding header. > > Patch 3: Add reset producer and consumer entries within the device tree. > > Patch 4: Add reset dm driver and bind it within prci module. > > Patch 5: Add Kconfig, Makefile entries and enable the driver > > > > This series is re-based on u-boot-riscv top commit 3b191c56c841 > > ("Merge branch '2020-07-28-Kconfig-migrations'") > > > > History: > > ========================== > > V5: > > -Rebased the series on u-boot-riscv/master. > > > > A gentle reminder to pull in this series. Applied to u-boot-riscv/master! Thanks, Rick