| Message ID | 1594919915-5225-3-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com |
|---|---|
| State | Not Applicable |
| Delegated to: | David Miller |
| Headers | show |
| Series | Add support for SATA/PCIe/USB2[3]/VIN/CSI on R8A774E1 | expand |
On Thu, Jul 16, 2020 at 06:18:17PM +0100, Lad Prabhakar wrote: > Add PCIe{0,1} device nodes for R8A774E1 SoC. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Hmm, doesn't apply on top of 5.8-rc6 for me. Is there a branch to pull for easier review?
On Wed, Jul 22, 2020 at 10:58:49AM +0200, Wolfram Sang wrote: > On Thu, Jul 16, 2020 at 06:18:17PM +0100, Lad Prabhakar wrote: > > Add PCIe{0,1} device nodes for R8A774E1 SoC. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > Hmm, doesn't apply on top of 5.8-rc6 for me. Is there a branch to pull > for easier review? My fault, I missed the first series. Please note such dependencies in the cover letter.
Hi Wolfram, On Wed, Jul 22, 2020 at 10:00 AM Wolfram Sang <wsa@kernel.org> wrote: > > On Wed, Jul 22, 2020 at 10:58:49AM +0200, Wolfram Sang wrote: > > On Thu, Jul 16, 2020 at 06:18:17PM +0100, Lad Prabhakar wrote: > > > Add PCIe{0,1} device nodes for R8A774E1 SoC. > > > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> > > > > Hmm, doesn't apply on top of 5.8-rc6 for me. Is there a branch to pull > > for easier review? > > My fault, I missed the first series. Please note such dependencies in > the cover letter. > I didn't mention as they were already applied to Geert's tree [1] [1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git/log/?h=renesas-arm-dt-for-v5.9 Cheers, --Prabhakar
On Thu, Jul 16, 2020 at 7:18 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Add PCIe{0,1} device nodes for R8A774E1 SoC. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.10. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi index 001874af8cf2..5805541b7882 100644 --- a/arch/arm64/boot/dts/renesas/r8a774e1.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a774e1.dtsi @@ -1517,12 +1517,57 @@ }; pciec0: pcie@fe000000 { + compatible = "renesas,pcie-r8a774e1", + "renesas,pcie-rcar-gen3"; reg = <0 0xfe000000 0 0x80000>; #address-cells = <3>; #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>, + <0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>, + <0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>, + <0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 319>; status = "disabled"; + }; - /* placeholder */ + pciec1: pcie@ee800000 { + compatible = "renesas,pcie-r8a774e1", + "renesas,pcie-rcar-gen3"; + reg = <0 0xee800000 0 0x80000>; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000>, + <0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000>, + <0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000>, + <0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>; + /* Map all possible DDR as inbound ranges */ + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0>; + interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>; + clock-names = "pcie", "pcie_bus"; + power-domains = <&sysc R8A774E1_PD_ALWAYS_ON>; + resets = <&cpg 318>; + status = "disabled"; }; hdmi0: hdmi@fead0000 {
Add PCIe{0,1} device nodes for R8A774E1 SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> --- arch/arm64/boot/dts/renesas/r8a774e1.dtsi | 47 ++++++++++++++++++++++- 1 file changed, 46 insertions(+), 1 deletion(-)