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[committed] amdgcn: use unsigned extend for lshiftrt

Message ID 341b1c9b-4932-7396-876e-be42f84d2d5b@codesourcery.com
State New
Headers show
Series [committed] amdgcn: use unsigned extend for lshiftrt | expand

Commit Message

Andrew Stubbs May 15, 2020, 10:37 a.m. UTC 
This patch fixes a bug in which 8 and 16-bit vector shifts used the 
wrong kind of extend, thus causing wrong results.  It was simply a 
thinko in the insn code, so easily fixed.

Andrew


P.S. Apologies for the "work-in-progress" tag on the commit subject. 
Obviously that was meant to be removed, but I didn't notice it until 
after the push. :-(

Comments

Andrew Stubbs June 15, 2020, 12:46 p.m. UTC | #1 
On 15/05/2020 11:37, Andrew Stubbs wrote:
> This patch fixes a bug in which 8 and 16-bit vector shifts used the 
> wrong kind of extend, thus causing wrong results.  It was simply a 
> thinko in the insn code, so easily fixed.

This is now back-ported to releases/gcc-10.

Andrew
diff mbox series

Patch

WIP amdgcn: use unsigned extend for lshiftrt

This fixes a wrong-code logic error in a previous patch.
Detected by gcc.c-torture/execute/pr53645-2.c.

2020-05-15  Andrew Stubbs  <ams@codesourcery.com>

	gcc/
	* config/gcn/gcn-valu.md (v<expander><mode>3): Fix unsignedp.

diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md
index a43d6b6c6f3..d31fe5063b9 100644
--- a/gcc/config/gcn/gcn-valu.md
+++ b/gcc/config/gcn/gcn-valu.md
@@ -2113,7 +2113,7 @@ 
   ""
   {
     enum {ashift, lshiftrt, ashiftrt};
-    bool unsignedp = (<code> == ashift || <code> == ashiftrt);
+    bool unsignedp = (<code> == lshiftrt);
     rtx insi1 = gen_reg_rtx (<VnSI>mode);
     rtx insi2 = gen_reg_rtx (<VnSI>mode);
     rtx outsi = gen_reg_rtx (<VnSI>mode);