@@ -697,6 +697,8 @@ __altivec_scalar_pred(vec_any_nle,
/* Overloaded built-in functions for future architecture. */
#define vec_gnb(a, b) __builtin_vec_gnb (a, b)
+#define vec_clrl(a, b) __builtin_vec_clrl (a, b)
+#define vec_clrr(a, b) __builtin_vec_clrr (a, b)
#endif
#endif /* _ALTIVEC_H */
@@ -166,6 +166,8 @@ (define_c_enum "unspec"
UNSPEC_VGNB
UNSPEC_VPDEPD
UNSPEC_VPEXTD
+ UNSPEC_VCLRLB
+ UNSPEC_VCLRRB
])
(define_c_enum "unspecv"
@@ -4156,6 +4158,33 @@ (define_insn "vgnb"
"vgnb %0,%1,%2"
[(set_attr "type" "vecsimple")])
+(define_insn "vclrlb"
+ [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
+ (unspec:V16QI [(match_operand:V16QI 1 "altivec_register_operand" "v")
+ (match_operand:SI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VCLRLB))]
+ "TARGET_FUTURE"
+{
+ if (BYTES_BIG_ENDIAN)
+ return "vclrlb %0,%1,%2";
+ else
+ return "vclrrb %0,%1,%2";
+}
+ [(set_attr "type" "vecsimple")])
+
+(define_insn "vclrrb"
+ [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
+ (unspec:V16QI [(match_operand:V16QI 1 "altivec_register_operand" "v")
+ (match_operand:SI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VCLRRB))]
+ "TARGET_FUTURE"
+{
+ if (BYTES_BIG_ENDIAN)
+ return "vclrrb %0,%1,%2";
+ else
+ return "vclrlb %0,%1,%2";
+}
+ [(set_attr "type" "vecsimple")])
(define_expand "bcd<bcd_add_sub>_<code>"
[(parallel [(set (reg:CCFP CR6_REGNO)
@@ -2579,6 +2579,8 @@ BU_FUTURE_MISC_2 (CNTLZDM, "cntlzdm", CONST, cntlzdm)
BU_FUTURE_MISC_2 (CNTTZDM, "cnttzdm", CONST, cnttzdm)
/* Future architecture vector built-ins. */
+BU_FUTURE_V_2 (VCLRLB, "vclrlb", CONST, vclrlb)
+BU_FUTURE_V_2 (VCLRRB, "vclrrb", CONST, vclrrb)
BU_FUTURE_V_2 (VCFUGED, "vcfuged", CONST, vcfuged)
BU_FUTURE_V_2 (VCLZDM, "vclzdm", CONST, vclzdm)
BU_FUTURE_V_2 (VCTZDM, "vctzdm", CONST, vctzdm)
@@ -2587,6 +2589,8 @@ BU_FUTURE_V_2 (VPEXTD, "vpextd", CONST, vpextd)
BU_FUTURE_V_2 (VGNB, "vgnb", CONST, vgnb)
/* Future architecture overloaded vector built-ins. */
+BU_FUTURE_OVERLOAD_2 (CLRL, "clrl")
+BU_FUTURE_OVERLOAD_2 (CLRR, "clrr")
BU_FUTURE_OVERLOAD_2 (GNB, "gnb")
@@ -5506,6 +5506,17 @@ const struct altivec_builtin_types altivec_overloaded_builtins[] = {
RS6000_BTI_INTSI, RS6000_BTI_INTSI },
/* FUTURE overloaded builtin functions, */
+ { FUTURE_BUILTIN_VEC_CLRL, FUTURE_BUILTIN_VCLRLB,
+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
+ { FUTURE_BUILTIN_VEC_CLRL, FUTURE_BUILTIN_VCLRLB,
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
+ RS6000_BTI_UINTSI, 0 },
+ { FUTURE_BUILTIN_VEC_CLRR, FUTURE_BUILTIN_VCLRRB,
+ RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_UINTSI, 0 },
+ { FUTURE_BUILTIN_VEC_CLRR, FUTURE_BUILTIN_VCLRRB,
+ RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI,
+ RS6000_BTI_UINTSI, 0 },
+
{ FUTURE_BUILTIN_VEC_GNB, FUTURE_BUILTIN_VGNB, RS6000_BTI_unsigned_long_long,
RS6000_BTI_unsigned_V16QI, RS6000_BTI_UINTQI, 0 },
{ FUTURE_BUILTIN_VEC_GNB, FUTURE_BUILTIN_VGNB, RS6000_BTI_unsigned_long_long,
@@ -2457,7 +2457,7 @@ (define_insn "parity<mode>2_cmpb"
[(set_attr "type" "popcnt")])
(define_insn "cfuged"
- [(set (match_operand:DI 0 "register_operand" "=r")
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
(unspec:DI [(match_operand:DI 1 "gpc_reg_operand" "r")
(match_operand:DI 2 "gpc_reg_operand" "r")]
UNSPEC_CFUGED))]
@@ -20760,6 +20760,30 @@ Perform a vector count trailing zeros under bit mask operation, as if
implemented by the Future @code{vctzdm} instruction.
@findex vec_ctzm
+@smallexample
+@exdent vector signed char
+@exdent vec_clrl (vector signed char a, unsigned int n)
+@exdent vector unsigned char
+@exdent vec_clrl (vector unsigned char a, unsigned int n)
+@end smallexample
+Clear the left-most @code{(16 - n)} bytes of vector argument @code{a}, as if
+implemented by the @code{vclrlb} instruction on a big-endian target
+and by the @code{vclrrb} instruction on a little-endian target. A
+value of @code{n} that is greater than 16 is treated as if it equaled 16.
+@findex vec_clrl
+
+@smallexample
+@exdent vector signed char
+@exdent vec_clrr (vector signed char a, unsigned int n)
+@exdent vector unsigned char
+@exdent vec_clrr (vector unsigned char a, unsigned int n)
+@end smallexample
+Clear the right-most @code{(16 - n)} bytes of vector argument @code{a}, as if
+implemented by the @code{vclrrb} instruction on a big-endian target
+and by the @code{vclrlb} instruction on a little-endian target. A
+value of @code{n} that is greater than 16 is treated as if it equaled 16.
+@findex vec_clrr
+
@smallexample
@exdent vector unsigned long long int
@exdent vec_gnb (vector unsigned char, const unsigned char)
new file mode 100644
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=future" } */
+
+#include <altivec.h>
+
+extern void abort (void);
+
+/* Vector string clear left-most bytes of unsigned char. */
+vector unsigned char
+clrl (vector unsigned char arg, int n)
+{
+ return vec_clrl (arg, n);
+}
+
+/* { dg-final { scan-assembler {\mvclrlb\M} { target be } } } */
+/* { dg-final { scan-assembler {\mvclrrb\M} { target le } } } */
new file mode 100644
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_future_hw } */
+/* { dg-options "-mdejagnu-cpu=future" } */
+
+#include <altivec.h>
+
+extern void abort (void);
+
+/* Vector string clear left-most bytes of unsigned char. */
+vector unsigned char
+clrl (vector unsigned char arg, int n)
+{
+ return vec_clrl (arg, n);
+}
+
+int main (int argc, char *argv [])
+{
+ vector unsigned char input0 =
+ { 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
+ 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
+ vector unsigned char expected0 =
+ { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0xc, 0xd, 0xe, 0xf, 0x11 };
+ vector unsigned char expected1 =
+ { 0x0, 0x0, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
+ 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
+ vector unsigned char expected2 =
+ { 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
+ 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
+
+ if (!vec_all_eq (clrl (input0, 5), expected0))
+ abort ();
+ if (!vec_all_eq (clrl (input0, 13), expected1))
+ abort ();
+ if (!vec_all_eq (clrl (input0, 19), expected2))
+ abort ();
+}
new file mode 100644
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=future" } */
+
+#include <altivec.h>
+
+extern void abort (void);
+
+/* Vector string clear left-most bytes of unsigned char. */
+vector signed char
+clrl (vector signed char arg, int n)
+{
+ return vec_clrl (arg, n);
+}
+
+/* { dg-final { scan-assembler {\mvclrlb\M} { target be } } } */
+/* { dg-final { scan-assembler {\mvclrrb\M} { target le } } } */
new file mode 100644
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_future_hw } */
+/* { dg-options "-mdejagnu-cpu=future" } */
+
+#include <altivec.h>
+
+extern void abort (void);
+
+/* Vector string clear left-most bytes of unsigned char. */
+vector signed char
+clrl (vector signed char arg, int n)
+{
+ return vec_clrl (arg, n);
+}
+
+int main (int argc, char *argv [])
+{
+ vector signed char input0 =
+ { 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
+ 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
+ vector signed char expected0 =
+ { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0xc, 0xd, 0xe, 0xf, 0x11 };
+ vector signed char expected1 =
+ { 0x0, 0x0, 0x0, 0x4, 0x5, 0x6, 0x7, 0x8,
+ 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
+ vector signed char expected2 =
+ { 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
+ 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
+
+ if (!vec_all_eq (clrl (input0, 5), expected0))
+ abort ();
+ if (!vec_all_eq (clrl (input0, 13), expected1))
+ abort ();
+ if (!vec_all_eq (clrl (input0, 19), expected2))
+ abort ();
+}
new file mode 100644
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=future" } */
+
+#include <altivec.h>
+
+extern void abort (void);
+
+/* Vector string clear right-most bytes of unsigned char. */
+vector unsigned char
+clrr (vector unsigned char arg, int n)
+{
+ return vec_clrr (arg, n);
+}
+
+/* { dg-final { scan-assembler {\mvclrrb\M} { target be } } } */
+/* { dg-final { scan-assembler {\mvclrlb\M} { target le } } } */
new file mode 100644
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_future_hw } */
+/* { dg-options "-mdejagnu-cpu=future" } */
+
+#include <altivec.h>
+
+extern void abort (void);
+
+/* Vector string clear right-most bytes of unsigned char. */
+vector unsigned char
+clrr (vector unsigned char arg, int n)
+{
+ return vec_clrr (arg, n);
+}
+
+int main (int argc, char *argv [])
+{
+ vector unsigned char input0 =
+ { 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
+ 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
+ vector unsigned char expected0 =
+ { 0x1, 0x2, 0x3, 0x4, 0x5, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
+ vector unsigned char expected1 =
+ { 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
+ 0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0x0, 0x0 };
+ vector unsigned char expected2 =
+ { 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
+ 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
+
+ if (!vec_all_eq (clrr(input0, 5), expected0))
+ abort ();
+ if (!vec_all_eq (clrr(input0, 13), expected1))
+ abort ();
+ if (!vec_all_eq (clrr(input0, 19), expected2))
+ abort ();
+}
new file mode 100644
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mdejagnu-cpu=future" } */
+
+#include <altivec.h>
+
+extern void abort (void);
+
+/* Vector string clear right-most bytes of unsigned char. */
+vector signed char
+clrr (vector signed char arg, int n)
+{
+ return vec_clrr (arg, n);
+}
+
+/* { dg-final { scan-assembler {\mvclrrb\M} { target be } } } */
+/* { dg-final { scan-assembler {\mvclrlb\M} { target le } } } */
new file mode 100644
@@ -0,0 +1,37 @@
+/* { dg-do run } */
+/* { dg-require-effective-target powerpc_future_hw } */
+/* { dg-options "-mdejagnu-cpu=future" } */
+
+#include <altivec.h>
+
+extern void abort (void);
+
+/* Vector string clear right-most bytes of unsigned char. */
+vector signed char
+clrr (vector signed char arg, int n)
+{
+ return vec_clrr (arg, n);
+}
+
+int main (int argc, char *argv [])
+{
+ vector signed char input0 =
+ { 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
+ 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
+ vector signed char expected0 =
+ { 0x1, 0x2, 0x3, 0x4, 0x5, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 };
+ vector signed char expected1 =
+ { 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
+ 0x9, 0xa, 0xb, 0xc, 0xd, 0x0, 0x0, 0x0 };
+ vector signed char expected2 =
+ { 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, 0x8,
+ 0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf, 0x11 };
+
+ if (!vec_all_eq (clrr (input0, 5), expected0))
+ abort ();
+ if (!vec_all_eq (clrr (input0, 13), expected1))
+ abort ();
+ if (!vec_all_eq (clrr (input0, 19), expected2))
+ abort ();
+}
From: Kelvin Nilsen <kelvin@gcc.gnu.org> Add new vector instructions to clear leftmost and rightmost bytes. Bootstrapped and tested on powerpc64le-unknown-linux-gnu with no regressions. Is this okay for master? Thanks, Bill [gcc] 2020-05-08 Kelvin Nilsen <kelvin@gcc.gnu.org> * config/rs6000/altivec.h (vec_clrl): New #define. (vec_clrr): Likewise. * config/rs6000/altivec.md (UNSPEC_VCLRLB): New constant. (UNSPEC_VCLRRB): Likewise. (vclrlb): New insn. (vclrrb): Likewise. * config/rs6000/rs6000-builtin.def (__builtin_altivec_vclrlb): New built-in function. (__builtin_altivec_vclrrb): Likewise. (__builtin_vec_clrl): New overloaded built-in function. (__builtin_vec_clrr): Likewise. * config/rs6000/rs6000-call.c (altivec_overloaded_builtins): Define overloaded forms of __builtin_vec_clrl and __builtin_vec_clrr. * doc/extend.texi (PowerPC AltiVec Built-in Functions Available for a Future Architecture): Add descriptions of vec_clrl and vec_clrr. [gcc/testsuite] 2020-05-08 Kelvin Nilsen <kelvin@gcc.gnu.org> * gcc.target/powerpc/vec-clrl-0.c: New. * gcc.target/powerpc/vec-clrl-1.c: New. * gcc.target/powerpc/vec-clrr-0.c: New. * gcc.target/powerpc/vec-clrr-1.c: New. --- gcc/config/rs6000/altivec.h | 2 + gcc/config/rs6000/altivec.md | 29 +++++++++++++++ gcc/config/rs6000/rs6000-builtin.def | 4 ++ gcc/config/rs6000/rs6000-call.c | 11 ++++++ gcc/config/rs6000/rs6000.md | 2 +- gcc/doc/extend.texi | 24 ++++++++++++ gcc/testsuite/gcc.target/powerpc/vec-clrl-0.c | 16 ++++++++ gcc/testsuite/gcc.target/powerpc/vec-clrl-1.c | 37 +++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/vec-clrl-2.c | 16 ++++++++ gcc/testsuite/gcc.target/powerpc/vec-clrl-3.c | 37 +++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/vec-clrr-0.c | 16 ++++++++ gcc/testsuite/gcc.target/powerpc/vec-clrr-1.c | 37 +++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/vec-clrr-2.c | 16 ++++++++ gcc/testsuite/gcc.target/powerpc/vec-clrr-3.c | 37 +++++++++++++++++++ 14 files changed, 283 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-clrl-0.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-clrl-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-clrl-2.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-clrl-3.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-clrr-0.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-clrr-1.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-clrr-2.c create mode 100644 gcc/testsuite/gcc.target/powerpc/vec-clrr-3.c