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[PATCHv7,0/5] clk: agilex: add clock driver

Message ID 20200415164642.29382-1-dinguyen@kernel.org
Headers show
Series clk: agilex: add clock driver | expand

Message

Dinh Nguyen April 15, 2020, 4:46 p.m. UTC 
Hi,

This is version 7 of the patchset to add a clock driver to the Agilex
platform.

The change from v6 is to correct the dt-bindings document to include the
license header to be "(GPL-2.0-only OR BSD-2-Clause)".

Thanks,

Dinh Nguyen (5):
  clk: socfpga: stratix10: use new parent data scheme
  clk: socfpga: remove clk_ops enable/disable methods
  clk: socfpga: add const to _ops data structures
  dt-bindings: documentation: add clock bindings information for Agilex
  clk: socfpga: agilex: add clock driver for the Agilex platform

 .../bindings/clock/intel,agilex.yaml          |  46 ++
 drivers/clk/Makefile                          |   3 +-
 drivers/clk/socfpga/Makefile                  |   2 +
 drivers/clk/socfpga/clk-agilex.c              | 454 ++++++++++++++++++
 drivers/clk/socfpga/clk-gate-s10.c            |   5 +-
 drivers/clk/socfpga/clk-periph-s10.c          |  10 +-
 drivers/clk/socfpga/clk-pll-a10.c             |   4 +-
 drivers/clk/socfpga/clk-pll-s10.c             |  78 ++-
 drivers/clk/socfpga/clk-pll.c                 |   4 +-
 drivers/clk/socfpga/clk-s10.c                 | 160 ++++--
 drivers/clk/socfpga/stratix10-clk.h           |  10 +-
 include/dt-bindings/clock/agilex-clock.h      |  70 +++
 12 files changed, 794 insertions(+), 52 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml
 create mode 100644 drivers/clk/socfpga/clk-agilex.c
 create mode 100644 include/dt-bindings/clock/agilex-clock.h

Comments

Dinh Nguyen April 27, 2020, 3:43 p.m. UTC | #1 
Hi Stephen,

Was wondering if you have any comments on this series?

On 4/15/20 11:46 AM, Dinh Nguyen wrote:
> Hi,
> 
> This is version 7 of the patchset to add a clock driver to the Agilex
> platform.
> 
> The change from v6 is to correct the dt-bindings document to include the
> license header to be "(GPL-2.0-only OR BSD-2-Clause)".
> 
> Thanks,
> 
> Dinh Nguyen (5):
>   clk: socfpga: stratix10: use new parent data scheme
>   clk: socfpga: remove clk_ops enable/disable methods
>   clk: socfpga: add const to _ops data structures
>   dt-bindings: documentation: add clock bindings information for Agilex
>   clk: socfpga: agilex: add clock driver for the Agilex platform
> 
>  .../bindings/clock/intel,agilex.yaml          |  46 ++
>  drivers/clk/Makefile                          |   3 +-
>  drivers/clk/socfpga/Makefile                  |   2 +
>  drivers/clk/socfpga/clk-agilex.c              | 454 ++++++++++++++++++
>  drivers/clk/socfpga/clk-gate-s10.c            |   5 +-
>  drivers/clk/socfpga/clk-periph-s10.c          |  10 +-
>  drivers/clk/socfpga/clk-pll-a10.c             |   4 +-
>  drivers/clk/socfpga/clk-pll-s10.c             |  78 ++-
>  drivers/clk/socfpga/clk-pll.c                 |   4 +-
>  drivers/clk/socfpga/clk-s10.c                 | 160 ++++--
>  drivers/clk/socfpga/stratix10-clk.h           |  10 +-
>  include/dt-bindings/clock/agilex-clock.h      |  70 +++
>  12 files changed, 794 insertions(+), 52 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex.yaml
>  create mode 100644 drivers/clk/socfpga/clk-agilex.c
>  create mode 100644 include/dt-bindings/clock/agilex-clock.h
> 

Thanks,
Dinh