| Message ID | 20200421050622.8113-1-dianders@chromium.org |
|---|---|
| Headers | show |
| Series | drm: Prepare to use a GPIO on ti-sn65dsi86 for Hot Plug Detect | expand |
Quoting Douglas Anderson (2020-04-20 22:06:17) > The ti-sn65dsi86 MIPI DSI to eDP bridge chip has 4 pins on it that can > be used as GPIOs in a system. Each pin can be configured as input, > output, or a special function for the bridge chip. These are: > - GPIO1: SUSPEND Input > - GPIO2: DSIA VSYNC > - GPIO3: DSIA HSYNC or VSYNC > - GPIO4: PWM > > Let's expose these pins as GPIOs. A few notes: > - Access to ti-sn65dsi86 is via i2c so we set "can_sleep". > - These pins can't be configured for IRQ. > - There are no programmable pulls or other fancy features. > - Keeping the bridge chip powered might be expensive. The driver is > setup such that if all used GPIOs are only inputs we'll power the > bridge chip on just long enough to read the GPIO and then power it > off again. Setting a GPIO as output will keep the bridge powered. > - If someone releases a GPIO we'll implicitly switch it to an input so > we no longer need to keep the bridge powered for it. > > Becaue of all of the above limitations we just need to implement a Because > bare-bones GPIO driver. The device tree bindings already account for > this device being a GPIO controller so we only need the driver changes > for it. > > NOTE: Despite the fact that these pins are nominally muxable I don't > believe it makes sense to expose them through the pinctrl interface as > well as the GPIO interface. The special functions are things that the > bridge chip driver itself would care about and it can just configure > the pins as needed. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > Cc: Linus Walleij <linus.walleij@linaro.org> > Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> > --- > Cool patch. > Changes in v2: > - ("Export...GPIOs") is 1/2 of replacement for ("Allow...bridge GPIOs") > > drivers/gpu/drm/bridge/ti-sn65dsi86.c | 165 ++++++++++++++++++++++++++ > 1 file changed, 165 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > index 6ad688b320ae..d04c2b83d699 100644 > --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > @@ -874,6 +886,153 @@ static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata) > return 0; > } > > +static struct ti_sn_bridge *gchip_to_pdata(struct gpio_chip *chip) > +{ > + return container_of(chip, struct ti_sn_bridge, gchip); > +} > + > +static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip, > + unsigned int offset) > +{ > + struct ti_sn_bridge *pdata = gchip_to_pdata(chip); > + > + return (atomic_read(&pdata->gchip_output) & BIT(offset)) ? Any reason this isn't a bitmap? > + GPIOF_DIR_OUT : GPIOF_DIR_IN; And why can't we read the hardware to figure out if it's in output or input mode? > +} > + [...] > +static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip, > + unsigned int offset, int val) > +{ > + struct ti_sn_bridge *pdata = gchip_to_pdata(chip); > + int shift = offset * 2; > + int old_gchip_output; > + int ret; > + > + old_gchip_output = atomic_fetch_or(BIT(offset), &pdata->gchip_output); I presume gpiolib is already preventing a gpio from being modified twice at the same time. So is this atomic stuff really necessary? > + if (old_gchip_output & BIT(offset)) > + return 0; > + > + pm_runtime_get_sync(pdata->dev); > + > + /* Set value first to avoid glitching */ > + ti_sn_bridge_gpio_set(chip, offset, val); > + > + /* Set direction */ > + ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, > + 0x3 << shift, SN_GPIO_MUX_OUTPUT << shift); > + if (ret) { > + atomic_andnot(BIT(offset), &pdata->gchip_output); > + pm_runtime_put(pdata->dev); > + } > + > + return ret; > +} > + > +static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset) > +{ > + /* We won't keep pm_runtime if we're input, so switch there on free */ > + ti_sn_bridge_gpio_direction_input(chip, offset); > +} > + > +static const char * const ti_sn_bridge_gpio_names[] = { > + "GPIO1", "GPIO2", "GPIO3", "GPIO4" > +}; > + > +static int ti_sn_setup_gpio_controller(struct ti_sn_bridge *pdata) > +{ [...] > + pdata->gchip.names = ti_sn_bridge_gpio_names; > + pdata->gchip.ngpio = ARRAY_SIZE(ti_sn_bridge_gpio_names); > + ret = devm_gpiochip_add_data(pdata->dev, &pdata->gchip, pdata); > + if (ret) { > + dev_err(pdata->dev, "can't add gpio chip\n"); > + return ret; > + } > + > + return 0; return ret? > +} > + > static int ti_sn_bridge_probe(struct i2c_client *client, > const struct i2c_device_id *id) > {
Quoting Douglas Anderson (2020-04-20 22:06:22) > We don't have the HPD line hooked up to the bridge chip. Add it as > suggested in the patch ("dt-bindings: drm/bridge: ti-sn65dsi86: > Document no-hpd"). > > NOTE: this patch isn't expected to have any effect but just keeps us > cleaner for the future. Currently the driver in Linux just assumes > that nobody has HPD hooked up. This change allows us to later > implement HPD support in the driver without messing up sdm845-cheza. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Hi, On Wed, Apr 22, 2020 at 3:23 AM Stephen Boyd <swboyd@chromium.org> wrote: > > Quoting Douglas Anderson (2020-04-20 22:06:17) > > The ti-sn65dsi86 MIPI DSI to eDP bridge chip has 4 pins on it that can > > be used as GPIOs in a system. Each pin can be configured as input, > > output, or a special function for the bridge chip. These are: > > - GPIO1: SUSPEND Input > > - GPIO2: DSIA VSYNC > > - GPIO3: DSIA HSYNC or VSYNC > > - GPIO4: PWM > > > > Let's expose these pins as GPIOs. A few notes: > > - Access to ti-sn65dsi86 is via i2c so we set "can_sleep". > > - These pins can't be configured for IRQ. > > - There are no programmable pulls or other fancy features. > > - Keeping the bridge chip powered might be expensive. The driver is > > setup such that if all used GPIOs are only inputs we'll power the > > bridge chip on just long enough to read the GPIO and then power it > > off again. Setting a GPIO as output will keep the bridge powered. > > - If someone releases a GPIO we'll implicitly switch it to an input so > > we no longer need to keep the bridge powered for it. > > > > Becaue of all of the above limitations we just need to implement a > > Because > > > bare-bones GPIO driver. The device tree bindings already account for > > this device being a GPIO controller so we only need the driver changes > > for it. > > > > NOTE: Despite the fact that these pins are nominally muxable I don't > > believe it makes sense to expose them through the pinctrl interface as > > well as the GPIO interface. The special functions are things that the > > bridge chip driver itself would care about and it can just configure > > the pins as needed. > > > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > > Cc: Linus Walleij <linus.walleij@linaro.org> > > Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> > > --- > > > > Cool patch. > > > Changes in v2: > > - ("Export...GPIOs") is 1/2 of replacement for ("Allow...bridge GPIOs") > > > > drivers/gpu/drm/bridge/ti-sn65dsi86.c | 165 ++++++++++++++++++++++++++ > > 1 file changed, 165 insertions(+) > > > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > > index 6ad688b320ae..d04c2b83d699 100644 > > --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c > > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > > @@ -874,6 +886,153 @@ static int ti_sn_bridge_parse_dsi_host(struct ti_sn_bridge *pdata) > > return 0; > > } > > > > +static struct ti_sn_bridge *gchip_to_pdata(struct gpio_chip *chip) > > +{ > > + return container_of(chip, struct ti_sn_bridge, gchip); > > +} > > + > > +static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip, > > + unsigned int offset) > > +{ > > + struct ti_sn_bridge *pdata = gchip_to_pdata(chip); > > + > > + return (atomic_read(&pdata->gchip_output) & BIT(offset)) ? > > Any reason this isn't a bitmap? Don't bitmaps need an external lock to protect against concurrent access? When I looked I wasn't convinced that the GPIO subsystem prevented two callers from changing two GPIOs at the same time. See below for a bigger discussion. > > + GPIOF_DIR_OUT : GPIOF_DIR_IN; > > And why can't we read the hardware to figure out if it's in output or > input mode? A few reasons: 1. If nobody else had the bridge powered on this would be a slow operation involving powering the bridge on, querying via i2c, and then powering the bridge off. Not only would it be slow but you'd be powering the chip up for no really good reason. You didn't need to know anything that only the chip could tell you. 2. If nobody else had the bridge powered on then the bridge loses state and resets to defaults (everything resets to "input"). Yes, we could still power the bridge up and confirm this, but... 3. This bitmap does double-duty of not only knowing whether a pin is input or output but also whether we've incremented the "pm_runtime" refcount in order to keep the output driven. Knowing whether we've already incremented the "pm_runtime" refcount can simplify a bit of the code because we know whether it's powered without having to power it on and query. If we didn't have a cache, then when we changed a pin to input we'd do: pm_runtime_get() // Make sure we can access if dir_was_output: pm_runtime_put() // Not driving anymore set_to_input(); pm_runtime_put() // Done with access ...basically in some cases we'd do pm_runtime_put() twice in the same function. It'd work, but feels like a worse solution than the one in my patch. 4. When I bootup I see that this call gets made once per GPIO in gpiochip_add_data_with_key(). There's no reason to go through all the slowness when we know these pins are inputs. In the next version of the patch I'll plan to add a kerneldoc comment to "struct ti_sn_bridge" and add a summary of the above for "gchip_output". > > +} > > + > [...] > > +static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip, > > + unsigned int offset, int val) > > +{ > > + struct ti_sn_bridge *pdata = gchip_to_pdata(chip); > > + int shift = offset * 2; > > + int old_gchip_output; > > + int ret; > > + > > + old_gchip_output = atomic_fetch_or(BIT(offset), &pdata->gchip_output); > > I presume gpiolib is already preventing a gpio from being modified twice > at the same time. So is this atomic stuff really necessary? Right. I've assumed that we're not running two of these functions at the same time for the same GPIO. I'm not convinced that the GPIO core enforces this but it seems like it'd be undefined behavior for a client to be, for instance, setting and changing direction for the same GPIO in two threads at the same time. Where simple I've tried to make it so it wouldn't horribly break if someone did some amount of concurrent access of the same pin but not every corner case is handled. Mostly I focused on making sure that I could never mess up keeping track of whether I incremented the "pm_runtime" refcount for a pin. One thing specifically I didn't handle: if we were midway through ti_sn_bridge_gpio_set(), we context switched out and someone changed us to an input, then we'd possibly do an unpowered regmap_update_bits() and timeout. What I do think is a sensible case to handle, though, is someone working with two different GPIOs exported by this controller at the same time. IIUC atomic_t allows me to only spend 1 bit per pin, have no lock, and still make sure these different consumers don't stomp on each other. NOTE: I did a quick trace for the call chain when using the "gpioget" command-line tool. I saw: - ti_sn_bridge_gpio_get() - gpio_chip_get_multiple() - gpiod_get_array_value_complex() - linehandle_ioctl() None of these appear to do any locking. There's sorta an implicit lock in that only one client can "request" a given GPIO at the same time so the assumption that we're somewhat protected against two concurrent accesses of the exact same GPIO is a bit justified. ...but nothing appears to protect us from concurrent accesses of different GPIOs. I also notice that other GPIO drivers seem to grab their own locks. If it makes the patch more palatable, I can get rid of all the atomic stuff and put in a big mutex? -Doug
Quoting Douglas Anderson (2020-04-20 22:06:19) > People use panel-simple when they have panels that are builtin to > their device. In these cases the HPD (Hot Plug Detect) signal isn't > really used for hotplugging devices but instead is used for power > sequencing. Panel timing diagrams (especially for eDP panels) usually > have the HPD signal in them and it acts as an indicator that the panel > is ready for us to talk to it. > > Sometimes the HPD signal is hooked up to a normal GPIO on a system. > In this case we need to poll it in the correct place to know that the > panel is ready for us. In some system designs the right place for > this is panel-simple. > > When adding this support, we'll account for the case that there might > be a circular dependency between panel-simple and the provider of the > GPIO. The case this was designed for was for the "ti-sn65dsi86" > bridge chip. If HPD is hooked up to one of the GPIOs provided by the > bridge chip then in our probe function we'll always get back > -EPROBE_DEFER. Let's handle this by allowing this GPIO to show up > late if we saw -EPROBE_DEFER during probe. May be worth mentioning that if there isn't an hpd-gpios property then we only try once during probe and then after that the prepare callback doesn't try again because the gpio_get_optional() APIs are used. I had to think about that for a minute. > > Signed-off-by: Douglas Anderson <dianders@chromium.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
As talked about in commit c2bfc223882d ("drm/bridge: ti-sn65dsi86: Remove the mystery delay"), the normal HPD pin on ti-sn65dsi86 is kinda useless, at least for embedded DisplayPort (eDP). However, despite the fact that the actual HPD pin on the bridge is mostly useless for eDP, the concept of HPD for eDP still makes sense. It allows us to optimize out a hardcoded delay that many panels need if HPD isn't hooked up. Panel timing diagrams show HPD as one of the events to measure timing from and we have to assume the worst case if we can't actually read HPD. One way to use HPD for eDP without using the mostly useless HPD pin on ti-sn65dsi86 is to route the panel's HPD somewhere else in the system, like to a GPIO. This works great because eDP panels aren't physically hotplugged. That means the debouncing logic that caused us problems wasn't really needed and a raw GPIO works great. As per the above, a smart board designer would realize the value of HPD and choose to route it to a GPIO somewhere on the board to avoid the silly sn65dsi86 debouncing. While said "smart designer" could theoretically route HPD anywhere on the board, a really smart designer would realize that there are several GPIOs on the bridge itself that are nearly useless for anything but this purpose and route HPD to one of those. This series of patches is intended to allow the scenario described above. This patch has been tested on a board that is not yet mainline. On the hardware I have: - Panel spec says HPD could take up to 200 ms to come up, so without HPD hooked up we need to delay 200 ms. - On my board the panel is powered by the same rail as the touchscreen. By chance of probe order the touchscreen comes up first. This means by the time we check HPD in ti_sn_bridge_enable() it's already up. Thus we can use the panel on 200 ms earlier. - If I measure HPD on this pane it comes up ~56 ms after the panel is powered. This means I can save 144 ms of delay. Side effects (though not main goals) of this series are: - ti-sn65dsi86 GPIOs are now exported in Linux. - ti-sn65dsi86 bindings are converted to yaml. - Common panel bindings now have "hpd-gpios" listed. - The simple-panel driver in Linux can delay in prepare based on "hpd-gpios" - ti-sn65dsi86 bindings (and current user) now specifies "no-hpd" if HPD isn't hooked up. Changes in v2: - ("Export...GPIOs") is 1/2 of replacement for ("Allow...bridge GPIOs") - ("dt-bindings: display: Add hpd-gpios to panel-common...") new for v2 - ("simple...hpd-gpios") is 1/2 of replacement for ("Allow...bridge GPIOs") - specification => specifier. - power up => power. - Added back missing suspend-gpios. - data-lanes and lane-polarities are are the right place now. - endpoints don't need to be patternProperties. - Specified more details for data-lanes and lane-polarities. - Added old example back in, fixing bugs in it. - Example i2c bus is just called "i2c", not "i2c1" now. - ("dt-bindings: drm/bridge: ti-sn65dsi86: Document no-hpd") new for v2. - ("arm64: dts: sdm845: Add "no-hpd" to sn65dsi86 on cheza") new for v2. Douglas Anderson (6): drm/bridge: ti-sn65dsi86: Export bridge GPIOs to Linux dt-bindings: display: Add hpd-gpios to panel-common bindings drm/panel-simple: Support hpd-gpios for delaying prepare() dt-bindings: drm/bridge: ti-sn65dsi86: Convert to yaml dt-bindings: drm/bridge: ti-sn65dsi86: Document no-hpd arm64: dts: sdm845: Add "no-hpd" to sn65dsi86 on cheza .../bindings/display/bridge/ti,sn65dsi86.txt | 87 ------ .../bindings/display/bridge/ti,sn65dsi86.yaml | 285 ++++++++++++++++++ .../bindings/display/panel/panel-common.yaml | 6 + arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 2 + drivers/gpu/drm/bridge/ti-sn65dsi86.c | 165 ++++++++++ drivers/gpu/drm/panel/panel-simple.c | 53 ++++ 6 files changed, 511 insertions(+), 87 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.txt create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,sn65dsi86.yaml