Message ID | 20200415160054.951-1-pali@kernel.org |
---|---|
Headers | show |
Series | PCI: aardvark: Fix support for Turris MOX and Compex wifi cards | expand |
W dniu 15.04.2020 o 18:00, Pali Rohár pisze: > This patch series fixes PCI aardvark controller to work on Turris MOX > with Compex WLE900VX (and also other ath10k) wifi cards. > > Patches are available also in my git repository in branch pci-aardvark: > https://git.kernel.org/pub/scm/linux/kernel/git/pali/linux.git/log/?h=pci-aardvark > > Pali Rohár (8): > PCI: aardvark: Set controller speed from Device Tree max-link-speed > dts: espressobin: Define max-link-speed for pcie0 > PCI: aardvark: Start link training immediately after enabling link > training > PCI: aardvark: Do not overwrite Link Status register and ASPM Control > bits in Link Control register > PCI: aardvark: Set final controller speed based on negotiated link > speed > PCI: aardvark: Add support for issuing PERST via GPIO > dts: aardvark: Route pcie reset pin to gpio function and define > reset-gpios for pcie > PCI: aardvark: Add FIXME for code which access > PCIE_CORE_CMD_STATUS_REG > > .../dts/marvell/armada-3720-espressobin.dtsi | 2 + > .../dts/marvell/armada-3720-turris-mox.dts | 4 - > arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 2 +- > drivers/pci/controller/pci-aardvark.c | 118 +++++++++++++++--- > 4 files changed, 106 insertions(+), 20 deletions(-) > For the whole series Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Pali, I tested this series with Compex WLE900VX and with a ASMedia SATA card. Both are visible with these patches. But if I enable the pci-driver in U-Boot, kernel reports "link never came up" fo the WLE900VX card. The SATA card works in this case. advk-pcie d0070000.pcie: issuing PERST via reset GPIO for 1ms advk-pcie d0070000.pcie: setup link speed to 2 advk-pcie d0070000.pcie: link never came up advk-pcie d0070000.pcie: setup link speed to 1 advk-pcie d0070000.pcie: link never came up We should try to somehow reset the whole PCIe controller in Linux. There are the PCIe Core Warm Reset and PCIe PHY Warm Reset register. I also think that maybe we should try to reset the whole PCI comphy. Marek