Message ID | 20200408154155.68310-2-andriy.shevchenko@linux.intel.com |
---|---|
State | New |
Headers | show |
Series | [v2,1/2] gpio: merrifield: Switch over to MSI interrupts | expand |
On Wed, Apr 8, 2020 at 5:41 PM Andy Shevchenko <andriy.shevchenko@linux.intel.com> wrote: > It's a bit hard to realize what the BAR1 is for and what is the layout > of the data in it. Be slightly more verbose to better show how GPIO and > IRQ bases are derived from the hardware. > > Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Patch applied. Yours, Linus Walleij
diff --git a/drivers/gpio/gpio-merrifield.c b/drivers/gpio/gpio-merrifield.c index 11e6ea70568a..706687fab634 100644 --- a/drivers/gpio/gpio-merrifield.c +++ b/drivers/gpio/gpio-merrifield.c @@ -443,8 +443,8 @@ static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id base = pcim_iomap_table(pdev)[1]; - irq_base = readl(base); - gpio_base = readl(sizeof(u32) + base); + irq_base = readl(base + 0 * sizeof(u32)); + gpio_base = readl(base + 1 * sizeof(u32)); /* Release the IO mapping, since we already get the info from BAR1 */ pcim_iounmap_regions(pdev, BIT(1));
It's a bit hard to realize what the BAR1 is for and what is the layout of the data in it. Be slightly more verbose to better show how GPIO and IRQ bases are derived from the hardware. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> --- v2: no change drivers/gpio/gpio-merrifield.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)